--- title: "PC based concrete purifying factory with 8255" subject: "Instrumentation II" chapter: 2 key: "semester_5/instrumentation_ii:concrete-purifying-ppi-4000h" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/concrete-purifying-ppi-4000h site: BCT Engineering --- # PC based concrete purifying factory with 8255 Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System - Asked in: 2071 Shrawan, 1+1+2+2+4 marks - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/concrete-purifying-ppi-4000h - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2 ## Question Assume that your group has decided to make a PC based instrumentation control system for automatic concrete purifying factory using an 8255 PPI card at base address 4000H in memory mapped I/O mode for controlling purpose. (a) List out the collected documents and components. (b) List out the different signals you need to derive and or can be connected directly to your interfacing circuit. (c) Draw minimum mapping circuits for the above system. (d) What are the addresses captured by your card? Generate the control word for the system. (e) Write a program module to read ten set of raw data from port A and port B; add the data and store the result starting from address 4040H. ## Short answer Base address 4000H in memory-mapped I/O; ports A and B are inputs, port C output, mode 0. Port addresses: A=4000H, B=4001H, C=4002H, control=4003H. Control word 92H. Program reads ten sets from ports A and B, adds them, and stores 16-bit results starting at 4040H. ## Answer #### Assumptions 8085 system, 8255 memory mapped at base 4000H. Sensors: pressure/level/moisture transducers through signal conditioning and an 8-bit ADC (two channels read by port A and port B). Outputs go through port C to valves and motors. RAM is available at 4040H onwards. #### (a) Documents and components - Documents: datasheets of 8085, 8255, ADC, sensors, decoder gates; plant specification; block and circuit diagrams; address map; flowchart; program listing; test and calibration sheets. - Components: 8085 CPU, 74LS373, 8255A, ADC0808/0804 (two), sensors with op-amp conditioner, ROM, RAM, 74LS30/74LS04 gates or 74LS138 decoder, opto-isolators, relay drivers, relays/valves/motors, crystal, reset circuit, power supply. #### (b) Signals - Directly connected: D0-D7 (AD0-AD7), RD', WR', RESET OUT -> RESET. - Derived: A0, A1 (latched low address) to 8255 A0, A1; CS' from decoding A15-A2 with IO/M (memory cycle); ALE for 74LS373; ADC start and EOC through port C. #### (c) Minimum mapping circuit 4000H = 0100 0000 0000 0000: only A14 is 1, so A14 is connected directly and all other lines must be 0. ```text A15, A13..A2 --[NOR]--+ (output 1 only if all these lines are 0) A14 ------------------+--[AND]--[NOT]--> CS' (low for 4000H-4003H) IO/M --[NOT]----------+ (IO/M = 0 in a memory cycle) 8255: D0-D7, RD', WR', A0, A1, RESET ``` #### (d) Addresses and control word Port A = **4000H**, Port B = **4001H**, Port C = **4002H**, Control = **4003H**. Port A input, port B input, port C upper and lower output, mode 0: D7=1, D6D5=00, D4=1, D3=0, D2=0, D1=1, D0=0 = 1001 0010 = **92H**. #### (e) Program: read ten sets, add A and B, store from 4040H ```text MVI A,92H STA 4003H ; initialise 8255 LXI H,4040H ; result pointer MVI C,0AH ; ten sets NEXT: LDA 4000H ; read port A MOV B,A LDA 4001H ; read port B ADD B ; A = A + B MOV M,A ; store low byte INX H MVI A,00H ACI 00H ; carry into A MOV M,A ; store carry byte (16-bit result) INX H DCR C JNZ NEXT HLT ``` Each sum is stored as two bytes (sum, carry), so the ten results occupy 4040H-4053H. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With base 4000H memory mapped, what are the port addresses? A. A=4000H, B=4002H, C=4004H, Control=4006H B. A=4000H, B=4001H, C=4002H, Control=4004H C. A=4000H, B=4001H, C=4002H, Control=4003H D. A=4003H, B=4002H, C=4001H, Control=4000H Answer: C. A1 A0 select consecutive registers starting at the base. (Key point: Address map) 2. Port A input, B input, C upper and lower output, mode 0. Control word? A. 91H B. 92H C. 9BH D. 82H Answer: B. D7=1, D4=1 (A in), D1=1 (B in), D3=0, D0=0 gives 1001 0010 = 92H. (Key point: Control word) 3. Which address pattern must the decoding produce for CS' at 4000H-4003H? A. A15-A2 = 1000 0000 0000 00 B. A15-A2 = 0100 0000 0000 00 in a memory cycle C. A7 = 1 only D. A15-A12 = 0001 Answer: B. 4000H = 0100 0000 0000 0000, with A1 A0 free for register select. (Key point: Circuit CS') 4. How does the program handle the sum of A and B? A. Adds them and stores the sum byte then the carry byte, so each result takes 2 bytes B. Stores only the low byte C. Subtracts B from A D. Stores the sums at 4000H Answer: A. Since the sum can exceed 255, a carry byte follows the sum, so ten results fill 4040H-4053H. (Key point: Program logic) ## Related in Instrumentation II - [Ice cream factory MBI with 8255 at 5000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aicecream-ppi-5000h) — Instrumentation II, chapter 2 - [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2 - [8255 at A0A0H: interface and control words](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-a0a0h-control-words) — Instrumentation II, chapter 2 - [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2 - [Technical benefits of 8255 PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-benefits) — Instrumentation II, chapter 2, asked 2× - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 ## Related in other subjects - [Memory-mapped I/O reduces address space](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ammio-address-space) — Computer Organization and Architecture, chapter 7 - [Address sequencing for control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencer) — Computer Organization and Architecture, chapter 3, asked 7× - [Address sequencing capabilities of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aaddress-sequencing-capabilities) — Computer Organization and Architecture, chapter 3 - [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4