---
title: "Reducing crosstalk in PCB routing"
subject: "Instrumentation II"
chapter: 8
key: "semester_5/instrumentation_ii:crosstalk-routing"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/crosstalk-routing
site: BCT Engineering
---

# Reducing crosstalk in PCB routing

Instrumentation II · Chapter 8: Circuit Layout

- Asked in: 2072 Kartik, 4 marks; 2076 Asoj, 4 marks; 2075 Chaitra, 3 marks; 2068 Baisakh (old course), 6 marks; 2075 Asoj, 4 marks (asked 5 times)
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/crosstalk-routing
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-8

## Question

How can crosstalk be reduced when routing signal traces on a PCB? Explain the guidelines.

## Short answer

Increase trace spacing (3W rule), keep parallel runs short, route adjacent layers orthogonally, and use a solid ground plane close to signal layers. Place guard traces between sensitive lines, slow edge rates with series resistors, and separate analog, digital, and clock signals.

## Answer

Crosstalk on a PCB is coupling between adjacent traces through mutual capacitance (I = C·dV/dt) and mutual inductance (V = M·dI/dt). It grows with fast edges, small spacing, long parallel length and height above the ground plane. The routing guidelines to reduce it are:

1. **Increase spacing:** follow the **3W rule**: keep centre-to-centre distance of at least three trace widths (edge spacing about 2W). This reduces coupling by about 70 percent; 10W gives about 98 percent.
2. **Shorten parallel runs:** avoid long parallel routing of aggressor and victim; route the clock and other fast signals separately.
3. **Use orthogonal routing** on adjacent layers (horizontal on one, vertical on the next) so coupled length is minimal.
4. **Use a solid ground plane close to the signal layer;** small height h reduces the fields spread between traces and keeps the return current under the trace.
5. **Guard traces:** place a grounded trace between sensitive lines, connected to ground with vias at both ends and at intervals (stitching, each less than λ/10).
6. **Reduce edge rate:** use the slowest logic family that satisfies timing; add small series resistors at the source.
7. **Separate groups:** keep clock, high-speed, analog, power and sensitive lines in separate regions; keep the victim lines short and low-impedance.
8. **Differential pairs:** route tightly coupled and balanced, so that the noise appears as common-mode.
9. **Terminate** lines to avoid reflections that add to crosstalk.
10. **Avoid stubs and use the shortest path;** do not route near board edges or connectors in parallel.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What does the 3W rule specify?
   A. Trace length three times the width
   B. Centre-to-centre spacing of at least three trace widths
   C. Three ground vias per trace
   D. Three layers between signals
   Answer: B. Keeping spacing at 3W (edge spacing about 2W) reduces coupling by about 70 percent. (Key point: 3W rule)

2. Why keep the signal layer close to a solid ground plane?
   A. Small height reduces fields spreading between traces and keeps the return under the trace
   B. It increases mutual inductance
   C. It lengthens parallel runs
   D. It reduces the need for spacing to zero
   Answer: A. A small height confines the field and keeps return current beneath the trace, lowering crosstalk. (Key point: Ground plane height)

3. How should a guard trace be connected?
   A. Left floating
   B. Connected to the signal source
   C. Grounded with vias at both ends and at intervals less than λ/10
   D. Connected to Vcc via a resistor only
   Answer: C. Stitching to ground at intervals makes the guard effective. (Key point: Guard trace stitching)

4. How does edge rate affect crosstalk?
   A. Faster edges reduce it
   B. Edge rate has no effect
   C. Slower edges (slowest logic family, series resistors) reduce it
   D. Only analog signals are affected
   Answer: C. Crosstalk depends on dV/dt and dI/dt, so slower edges couple less. (Key point: Edge rate)

## Related in Instrumentation II

- [Factors while routing signal traces on PCB](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aroute-factors) — Instrumentation II, chapter 8, asked 4×
- [Terminologies in routing signal traces](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arouting-terminologies) — Instrumentation II, chapter 8
- [Routing factors and avoiding crosstalk](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aroute-factors-crosstalk) — Instrumentation II, chapter 8
- [Routing rules for crosstalk and impedance matching](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arules-mismatch-crosstalk) — Instrumentation II, chapter 8, asked 3×