--- title: "Static and dynamic errors in DAC" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:dac-static-dynamic-errors" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac-static-dynamic-errors site: BCT Engineering --- # Static and dynamic errors in DAC Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2068 Baisakh (old course), 6 marks - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac-static-dynamic-errors - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question Write a short note on Static and Dynamic errors in Digital to Analog Converters. ## Short answer Static errors include offset, gain error, INL, and DNL; DNL < –1 LSB causes non-monotonicity. Dynamic errors comprise settling time to ±½ LSB, slew limiting, glitches at major carry transitions, overshoot, and harmonic distortion. Static errors affect DC accuracy, dynamic errors limit speed and signal quality. ## Answer DAC errors are of two kinds: **static errors**, which exist when the digital input is steady, and **dynamic errors**, which appear when the input changes. #### Static errors 1. **Offset error:** output is not zero for input code 0; the whole characteristic is shifted. Trimmed by an offset adjustment. 2. **Gain (full-scale) error:** deviation of the slope from the ideal; full-scale output is wrong. Trimmed by adjusting the reference. 3. **Integral nonlinearity (INL):** maximum deviation of the actual output from the ideal straight line. 4. **Differential nonlinearity (DNL):** deviation of each step from 1 LSB. DNL < -1 LSB makes the DAC **non-monotonic**. 5. **Monotonicity error:** the output decreases when the code increases. 6. **Drift:** change of offset and gain with temperature and time; supply sensitivity (PSRR). Causes: resistor mismatch in R-2R ladder, switch resistance, reference and op-amp errors. #### Dynamic errors 1. **Settling time:** time needed for the output to reach and stay within +/-1/2 LSB of the final value after a code change. It is limited by the op-amp bandwidth and capacitances. 2. **Slew rate limit:** large steps produce a slew-limited, not exponential, response. 3. **Glitches:** spikes at major carry changes (0111 1111 to 1000 0000) because switches change at different times; the glitch energy is measured in nV-s. Reduced by a deglitching sample-and-hold or by segmented DACs. 4. **Overshoot and ringing** of the output amplifier. 5. **Feedthrough** of the digital signals to the analog output. 6. **Clock jitter and harmonic distortion (THD), SNR, SFDR** in high-speed DACs. ```text Output ^ ___ overshoot | / \____ settling band +/- 1/2 LSB | / ------------ final value | __/ <- slew +----|------------|--------------> time code change settling time ``` Static errors determine accuracy of DC output; dynamic errors limit the speed and signal quality for waveform generation. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How are static and dynamic DAC errors distinguished? A. Static errors exist for a steady digital input, dynamic errors appear when the input changes B. Static errors need a clock, dynamic do not C. Static errors only occur at low temperature D. They are the same Answer: A. Offset, gain, INL, DNL are static; settling time, glitches and slew limits are dynamic. (Key point: Static vs dynamic) 2. What does DNL worse than -1 LSB cause? A. A larger full-scale B. A faster output C. Non-monotonic output D. Lower offset Answer: C. If a step is below -1 LSB the output decreases when the code increases. (Key point: Monotonicity) 3. Where do glitches mostly occur and why? A. At code 0000 0000 due to offset B. At major carry transitions such as 0111 1111 to 1000 0000, because switches change at different times C. Only at low frequency D. At constant codes due to noise Answer: B. At the major carry many bits switch at once with unequal delays, producing spikes; a deglitching S/H reduces them. (Key point: Glitches) 4. What is settling time? A. Time for the code to be loaded B. Time of the clock period C. Delay from power-on only D. Time for the output to reach and stay within +/-1/2 LSB of the final value after a code change Answer: D. It is limited by amplifier bandwidth and capacitances. (Key point: Settling time) ## Related in Instrumentation II - [Errors in ADC and DAC](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-dac-errors) — Instrumentation II, chapter 4, asked 7× - [DNL and INL errors in ADC and DAC](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adnl-inl) — Instrumentation II, chapter 4, asked 2× - [Digital transmission system; analog vs digital](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aanalog-digital-transmission-compare) — Instrumentation II, chapter 5 - [Analog and digital communication systems](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aanalog-digital-comm-systems) — Instrumentation II, chapter 5 - [Advantages of digital over analog transmission](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adigital-vs-analog-transmission-adv) — Instrumentation II, chapter 5 - [Why digitize analog signals](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Awhy-digitize) — Instrumentation II, chapter 4, asked 2× ## Related in other subjects - [Static and dynamic hazards and their elimination](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Astatic-dynamic-hazards) — Digital Logic, chapter 3, asked 2× - [Static vs dynamic mathematical model](https://www.bctengineer.com/question.md?key=semester_8%2Fsimulation_and_modeling%3Astatic-vs-dynamic-math-model) — Simulation and Modeling, chapter 2, asked 3× - [Static vs dynamic implementation of list](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Astatic-vs-dynamic-list-example) — Data Structure and Algorithm, chapter 3, asked 2× - [Static versus dynamic binding trade-offs](https://www.bctengineer.com/question.md?key=semester_3%2Fobject_oriented_programming%3Astatic-vs-dynamic-binding) — Object Oriented Programming, chapter 7