--- title: "Interfacing 10-bit DAC with 8085" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:dac10-8085" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac10-8085 site: BCT Engineering --- # Interfacing 10-bit DAC with 8085 Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2073 Chaitra, 4 marks; 2071 Shrawan, 4 marks (asked 2 times) - Video: [Interfacing 10-Bit DAC with 8085](https://www.youtube.com/watch?v=vkZTmACcgl8) — last-minute ratta maar - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac10-8085 - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question Explain the way you can interface a 10-bit DAC with 8085. ## Short answer Use two latches for the 10-bit word: high byte (D9–D2) at port 80H, low byte (D1,D0 in D7,D6) at port 81H. A third strobe at port 82H transfers both simultaneously to avoid glitches. Resolution is 5 V/1024 ≈ 4.88 mV. ## Answer A 10-bit DAC (for example AD7533 / DAC1020) needs a 10-bit input, but the 8085 data bus has only 8 bits, so the data must be written in **two bytes**. To avoid glitches (wrong intermediate output when one byte is updated before the other), a **double buffered** interface is used: input latches hold the two bytes, and a second rank of latches (or the DAC register) updates all 10 bits together. #### Data format (left justified) The 10-bit value D9...D0 is written as byte 1 = D9...D2 (8 bits) and byte 2 = D1 D0 in bit positions D7, D6 (the rest zero). #### Block diagram (I/O mapped) ```text 8085 D0-D7 ---> Latch 1 (74LS373) D9..D2 ---+ | clock: port 80H | | +--> Latch 3 (output +---> Latch 2 (74LS373) D1,D0 --+ register) ---> 10-bit clock: port 81H DAC (AD7533) Port 82H write pulse -> Latch 3 (updates all 10 bits together) IOW' + address decoder (74LS138): Y0 -> port 80H, Y1 -> port 81H, Y2 -> port 82H DAC output current -> op-amp (I to V converter) -> Vout ``` Resolution: with Vref = 5 V, one step = 5 / 1024 = 4.88 mV (1024 levels). #### Port addresses Latch 1 (high byte) = 80H, Latch 2 (low 2 bits) = 81H, update strobe = 82H. #### Program Value stored as high byte at 2050H and low bits (D7, D6) at 2051H: ```text LDA 2051H ; low 2 bits in D7, D6 OUT 81H ; load latch 2 LDA 2050H ; D9..D2 OUT 80H ; load latch 1 OUT 82H ; strobe: transfer both to DAC at same time HLT ``` The same method generates waveforms by repeating the sequence for a table of values. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why two writes? A. Address bus B. 10 bits but 8085 bus is 8 bits C. Two DACs D. Slow DAC Answer: B. Data in two bytes. (Key point: Two bytes) 2. Purpose of double buffering? A. Avoid glitches by updating all bits together B. Save memory C. More speed D. Less wiring Answer: A. Third latch updates both. (Key point: Double buffer) 3. Role of OUT 82H? A. Transfers both latches to DAC at once B. Halts C. Loads high byte D. Resets Answer: A. Update strobe. (Key point: Strobe) 4. Step with 5 V ref? A. 5/256 B. 5/4096 C. 5/10 D. 5/1024 = 4.88 mV Answer: D. 1024 levels. (Key point: Resolution) ## Related in Instrumentation II - [12-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac12-with-8085) — Instrumentation II, chapter 4, asked 2× - [10-bit DAC triangular wave at 500 Hz](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-triangular-500hz) — Instrumentation II, chapter 4 - [Interfacing 8-channel 8-bit ADC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc0808-8channel) — Instrumentation II, chapter 4 - [Interfacing 1408 DAC for 0 to 10 V](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac1408-0-10v) — Instrumentation II, chapter 4 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 ## Related in other subjects - [Bipolar DAC output and 3-bit transfer curve](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Abipolar-dac-transfer-curve) — Advanced Electronics, chapter 3 - [5-bit R-2R DAC output for 10110](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ar2r-5bit-10110) — Advanced Electronics, chapter 3 - [4-bit inverted R-2R DAC and why better](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Ainverted-r2r-4bit-better) — Advanced Electronics, chapter 3 - [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2