--- title: "10-bit DAC triangular wave at 500 Hz" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:dac10-triangular-500hz" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac10-triangular-500hz site: BCT Engineering --- # 10-bit DAC triangular wave at 500 Hz Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2075 Asoj, 8 marks - Video: [DAC INTERFACING- TRIANGULAR WAVE GENERATION USING IO MODE](https://www.youtube.com/watch?v=X03FVYMLlgY) — S Nazeer Hussain - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac10-triangular-500hz - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question Interface a 10-bit DAC with 8255 PPI and 8085 CPU running at 2 MHz. Write an ALP to generate a triangular wave of frequency 500 Hz using the same interfacing circuit. The amplitude of the triangular wave should be +5V. ## Short answer A 10-bit DAC is interfaced via 8255 ports A and B (control word 80H). The triangular wave is generated by ramping up and down in 32 steps of 32 codes each, with loop delays giving a frequency of ~504 Hz. Vref = 5 V yields a peak near 5 V. ## Answer #### Assumptions and interfacing The 10-bit DAC is of the AD7533 type (current output with an op-amp, Vref = 5 V so that full scale is about +5 V). The 8085 runs at 2 MHz (T = 0.5 us). The 8255 is I/O mapped at 80H-83H. The 10 data bits are: low 8 bits on **port A**, upper 2 bits on **PB1 PB0** (port B). ```text 8085 -- AD0-AD7, IOW', RESET, A0,A1, CS' -- 8255 8255 PA0-PA7 -------> DAC D7..D0 8255 PB0,PB1 -------> DAC D8, D9 DAC IOUT --> op-amp (current-to-voltage) --> Vout 0 to +5 V ``` Control word: ports A and B output, mode 0: 1000 0000 = **80H**. #### Timing A frequency of 500 Hz means a period of 2 ms: a ramp up of 1 ms and a ramp down of 1 ms (2000 T-states each). The 8085 cannot write all 1024 codes in 1 ms (it needs about 1 us per code), so each ramp is made of **32 steps** of 32 codes each (a step of 32 x 4.88 mV = 156 mV, small enough for a smooth triangle after a low-pass filter). Loop timing (T-states): up loop per step = MOV A,L (4) + OUT (10) + MOV A,H (4) + OUT (10) + DAD D (10) + MOV A,H (4) + CPI (7) + NOP (4) + JNZ (10) = 63. Down loop per step = DAD D (10) + 2 x (MOV + OUT = 14) + MOV A,H (4) + ORA L (4) + NOP (4) + JNZ (10) = 60. Total: up about 32 x 63 - 3 = 2013; down about 32 x 60 - 3 = 1917. The two LXI D (10 each), LXI H (10) and JMP (10) add 40. Cycle = 2013 + 1917 + 40 = 3970 T = 1.985 ms, so the frequency is **504 Hz** (about 500 Hz, error about 1%). #### Program ```text MVI A,80H OUT 83H ; ports A,B output START: LXI H,0000H ; 10-bit value in HL LXI D,0020H ; step +32 UP: MOV A,L OUT 80H ; low 8 bits MOV A,H OUT 81H ; upper 2 bits DAD D ; HL = HL + 32 MOV A,H CPI 04H ; reached 1024 ? NOP JNZ UP LXI D,FFE0H ; step -32 DOWN: DAD D ; HL = HL - 32 MOV A,L OUT 80H MOV A,H OUT 81H MOV A,H ORA L ; HL = 0 ? NOP JNZ DOWN JMP START ``` The peak code is 03E0H (992), which gives 992/1024 x 5 V = 4.84 V. Use Vref = 5.16 V (or add a final step of 03FFH) if the peak must be exactly 5 V. The output is a triangle from 0 to +5 V at about 500 Hz. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How are the 10 DAC data bits connected to the 8255? A. All 10 on port A B. Low 8 bits on port C C. Upper 2 bits on PA0 PA1 only D. Low 8 bits on port A, upper 2 bits on PB1 PB0 Answer: D. Port A carries D0-D7 and PB0, PB1 carry D8, D9. (Key point: Bit allocation) 2. Why is the ramp built from 32 steps of 32 codes rather than 1024 single steps? A. The 8085 cannot write all 1024 codes within 1 ms at 2 MHz B. The DAC only has 32 levels C. Because the control word demands it D. To increase the amplitude Answer: A. Each code needs about 1 us or more, so the CPU is too slow; larger steps are smoothed by a low-pass filter. (Key point: Why 32 steps) 3. Ports A and B output in mode 0 requires which control word? A. 90H B. 80H C. 98H D. 00H Answer: B. Only mode set bit D7 = 1 with all others 0: 80H. (Key point: Control word) 4. What is the peak output with the maximum code 03E0H and Vref = 5 V? A. 5.00 V B. 3.2 V C. 4.5 V D. About 4.84 V Answer: D. 992/1024 x 5 V = 4.84 V, so Vref about 5.16 V or a final step of 03FFH gives exactly 5 V. (Key point: Peak value) ## Related in Instrumentation II - [Interfacing 10-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-8085) — Instrumentation II, chapter 4, asked 2× - [DAC square wave generation at 1 kHz](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac-square-wave-1khz) — Instrumentation II, chapter 4 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [12-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac12-with-8085) — Instrumentation II, chapter 4, asked 2× - [Interfacing 8-channel 8-bit ADC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc0808-8channel) — Instrumentation II, chapter 4 - [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2 ## Related in other subjects - [8085 ALP: compare two tables of 16-bit data](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-compare-tables-1ffffh) — Microprocessor, chapter 2 - [8085 ALP: odd parity transfer with bit change](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-odd-parity-transfer) — Microprocessor, chapter 2 - [8085 ALP: transfer with bit set/reset](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-set-reset-bit-80h) — Microprocessor, chapter 2 - [Load sharing: 250/500 MW, frequency falls to 49.5 Hz](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Aload-sharing-250-500-4-2) — Power Plant Equipment, chapter 2, asked 2×