--- title: "12-bit DAC with 8085" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:dac12-with-8085" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac12-with-8085 site: BCT Engineering --- # 12-bit DAC with 8085 Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2071 Chaitra, 6 marks; 2075 Chaitra, 6 marks (asked 2 times) - Video: [lecture 9, Interfacing an 8 bit DAC convertern with Microprocessor](https://www.youtube.com/watch?v=DEQVh3cNA7k) — Electronics Pedia - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dac12-with-8085 - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question How can you design a 12-bit DAC interface with an 8-bit data bus microprocessor (8085)? Explain with a suitable block diagram. ## Short answer Write upper 8 bits (D11–D4) to port 80H, lower 4 bits (D3–D0) to port 81H, then strobe port 82H to transfer both latches to the DAC register at once, preventing glitches. Resolution is Vref/4096, e.g., 2.44 mV for 10 V. ## Answer A 12-bit DAC (for example DAC1208 / AD7545) has 12 inputs, but the 8085 has an 8-bit data bus. The CPU writes the 12-bit word in **two bytes** into **two input latches**, and then transfers both to the **DAC register** in one operation, so the output changes only once and glitches are avoided. #### DAC1208 arrangement - First write: **upper 8 bits (D11-D4)** into the 8-bit input latch (BYTE1/BYTE2' = 1, WR1'). - Second write: **lower 4 bits (D3-D0)** into the 4-bit input latch (BYTE1/BYTE2' = 0). Data is left justified in D7-D4 of the bus. - Third write: XFER' and WR2' pulse moves both latches into the 12-bit DAC register, which drives the converter. #### Block diagram (I/O mapped, ports 80H-82H) ```text 8085 DAC1208 AD0-AD7 (D0-D7) --------> DI4-DI11 (8-bit latch) & DI0-DI3 (4-bit) IOW' --------------------> WR1', WR2' Decoder (74LS138): port 80H (A0=0) -------> CS', BYTE1/BYTE2' = 1 (high byte) port 81H --------------> CS', BYTE1/BYTE2' = 0 (low nibble) port 82H --------------> XFER' (transfer to DAC register) DAC IOUT1, IOUT2 -> op-amp (current to voltage) -> Vout Vref = 10 V: 1 LSB = 10 / 4096 = 2.44 mV ``` Output Vout = -Vref x (N / 4096) for a standard current-to-voltage amplifier. #### Program (12-bit value in HL: H = D11-D4, L = D3-D0 in the upper nibble) ```text MOV A,H OUT 80H ; high 8 bits to latch 1 MOV A,L OUT 81H ; low 4 bits (D7-D4) to latch 2 OUT 82H ; transfer to DAC register RET ``` Example: for the 12-bit value 0ABCH, H = ABH (D11-D4) and L = C0H (D3-D0 in the upper nibble). With the two-level latching the analog output changes only once for each complete word. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is 12-bit sent? A. One write B. Three DACs C. Two bytes into input latches, then transfer to DAC register D. Serial Answer: C. Two input latches then DAC register. (Key point: Latch plan) 2. First write contains? A. All 12 B. D7-D0 of 8085 C. D3-D0 D. D11-D4 Answer: D. Upper 8 bits. (Key point: Upper byte) 3. Role of XFER'? A. Chip select B. Moves both latches into DAC register C. Clock D. Reset Answer: B. One update. (Key point: XFER) 4. 1 LSB with 10 V ref? A. 10/256 B. 10/4096 = 2.44 mV C. 10/1024 D. 10/12 Answer: B. 4096 levels. (Key point: LSB) ## Related in Instrumentation II - [Interfacing 10-bit DAC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-8085) — Instrumentation II, chapter 4, asked 2× - [10-bit DAC triangular wave at 500 Hz](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac10-triangular-500hz) — Instrumentation II, chapter 4 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [Interfacing 8-channel 8-bit ADC with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc0808-8channel) — Instrumentation II, chapter 4 - [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6× - [Compact data logger characteristics and block diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acompact-dl-block) — Instrumentation II, chapter 5 ## Related in other subjects - [8085 ALP: compare two tables of 16-bit data](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-compare-tables-1ffffh) — Microprocessor, chapter 2 - [n-bit full adder block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3An-bit-full-adder) — Digital Logic, chapter 5 - [Microprocessor based system and bus organization](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amp-based-system-bus-organization) — Microprocessor, chapter 1, asked 5× - [Design 4-bit R-2R DAC; unipolar vs bipolar](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adesign-4bit-r2r-unipolar-bipolar) — Advanced Electronics, chapter 3