--- title: "Data logger input scanner and conditioner design" subject: "Instrumentation II" chapter: 5 key: "semester_5/instrumentation_ii:datalogger-three-transducers" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/datalogger-three-transducers site: BCT Engineering --- # Data logger input scanner and conditioner design Instrumentation II · Chapter 5: Data Acquisition And Transmission - Asked in: 2074 Asoj, 3+3 marks - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/datalogger-three-transducers - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-5 ## Question Signals from three different transducers need to be recorded in a data logger. The analog signals supplied by the three transducers are dual polarity (-50 mV to 50 mV) having frequencies of 5 KHz, 10 KHz and 15 KHz. Explain the design of the following stages of the data logger: (a) Input scanner stage of the data logger such that it can appropriately sample the incoming signals. (b) Signal conditioner stage if the 8-bit ADC used inside the data logger accepts only positive polarity signals ranging from 0 volts to 5 volts. ## Short answer For the scanner, use a multiplexer with per-channel sampling rate of 40 kHz (scan rate 120 kHz) and anti-alias filters at 16 kHz. The signal conditioner must amplify by 50 and add a 2.5 V offset to map ±50 mV to 0–5 V, using an instrumentation amplifier and a summing stage. ## Answer #### Given Three transducer outputs, each +/-50 mV (100 mV span), with frequencies 5, 10 and 15 kHz. ADC: 8-bit, accepts 0 to 5 V. #### (a) Input scanner stage The input scanner is an analog multiplexer (CD4051/DG408, 8 channels) controlled by the logger's controller; it connects each transducer to the S/H and ADC in turn. 1. **Sampling rate per channel:** by the Nyquist theorem, fs >= 2 x fmax = 2 x 15 kHz = 30 kHz. Choose **40 kHz** per channel (a margin for the anti-alias filter roll-off) for all three channels so that each is sampled correctly. 2. **Scanning rate:** 3 channels x 40 kHz = **120 kHz**, so each channel slot is 1 / 120 kHz = **8.33 us**. The S/H acquisition time + ADC conversion time must be less than 8.33 us (fast SAR or flash ADC such as ADC0820, 1.5 us conversion; the S/H must have an acquisition time below 3 us). 3. Use an **anti-alias low-pass filter** (cut-off about 16 kHz, 4th order) at each channel input, before the multiplexer. 4. Use a **sample-and-hold** (one common after the MUX, or one per channel for simultaneous sampling) with aperture time much smaller than the period; for 15 kHz and an amplified 2.5 V peak and 8 bits: Dt <= (LSB/2)/(2 pi f A) = 9.8 mV / (2 pi x 15e3 x 2.5) = 41 ns. 5. Channel selection by counter or controller: address lines A0, A1 of the MUX step through 0, 1, 2 repeatedly. ```text T1 -> [LPF 16k] -+ T2 -> [LPF 16k] -+-> [4051 MUX] -> [S/H] -> to conditioner/ADC T3 -> [LPF 16k] -+ ^ select (counter, 120 kHz) ``` #### (b) Signal conditioner stage The ADC accepts only 0 to 5 V, but the signal is -50 mV to +50 mV. Both **amplification** and **level shifting** are needed. - Gain = output span / input span = 5 V / 0.1 V = **50**. - Offset: -50 mV must give 0 V, +50 mV must give 5 V, so the mid-point 0 V must give 2.5 V. Therefore Vout = 50 x Vin + 2.5 V. - Check: Vin = -50 mV -> 0 V; Vin = 0 -> 2.5 V; Vin = +50 mV -> 5 V. ```text Vin -> [Instrumentation amp, gain 50] -> [Summing amp: +2.5 V] -> ADC (INA114, Rg = 1.02 kohm) (2.5 V from a reference IC) ``` Implementation: an instrumentation amplifier INA114 with Rg = 50 kohm/(G - 1) = 1.02 kohm gives gain 50 with good common-mode rejection. The second stage is a summing amplifier (or a differential amplifier with reference) which adds a dc level of +2.5 V from a precision reference (REF02 + divider). Clamp diodes at the ADC input and a final low-pass filter protect the ADC. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What minimum sampling rate per channel is needed for the signals of up to 15 kHz? A. 15 kHz B. 10 kHz C. 30 kHz (twice the highest frequency) D. 45 kHz Answer: C. By Nyquist, fs >= 2 x 15 kHz = 30 kHz; 40 kHz is chosen with margin. (Key point: Sampling rate) 2. If each of 3 channels is sampled at 40 kHz, what is the scanning rate and slot time? A. 40 kHz and 25 us B. 80 kHz and 12.5 us C. 120 kHz and 83.3 us D. 120 kHz and about 8.33 us Answer: D. 3 x 40 kHz = 120 kHz, and 1/120 kHz = 8.33 us per slot. (Key point: Scanning rate) 3. What gain is needed to map a 100 mV span to the 0-5 V ADC range? A. 50 B. 5 C. 100 D. 25 Answer: A. Gain = 5 V / 0.1 V = 50. (Key point: Signal conditioner gain) 4. What dc offset is added after amplification so -50 mV to +50 mV maps to 0-5 V? A. +5 V B. +2.5 V, since Vout = 50 Vin + 2.5 C. -2.5 V D. 0 V, no offset needed Answer: B. The zero-input midpoint must land at 2.5 V, so -50 mV gives 0 V and +50 mV gives 5 V. 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