---
title: "DMA active and idle cycles"
subject: "Instrumentation II"
chapter: 1
key: "semester_5/instrumentation_ii:dma-cycles-disadvantages"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dma-cycles-disadvantages
site: BCT Engineering
---

# DMA active and idle cycles

Instrumentation II · Chapter 1: Microprocessor Based Instrumentation System

- Asked in: 2078 Kartik, 2+2 marks
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dma-cycles-disadvantages
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-1

## Question

Describe the DMA active and idle cycles with appropriate figures. Provide at least five disadvantages of using DMA controllers.

## Short answer

Idle cycle: DMAC samples DREQ, CPU controls bus. Active cycle: DMAC requests bus via HOLD, gets HLDA, transfers byte/block, then releases bus. Disadvantages: extra hardware cost, complex programming, CPU halted during transfers, overhead for small moves, risk of memory corruption by bad addresses, cache coherence issues.

## Answer

In a DMA system the bus is used by either the CPU or the DMA controller (DMAC), so operation alternates between **idle** and **active** cycles.

- **Idle cycle:** the DMAC has no request (no DREQ) or has no bus. The CPU owns the bus and executes its program. The DMAC only samples DREQ lines.
- **Active cycle:** after DREQ, the DMAC sends HOLD, receives HLDA, and then controls the buses. It transfers one byte (cycle stealing), a block (burst) or until the CPU needs the bus. After the transfer, HOLD is released and the CPU resumes.

```text
 Time ->
 CPU bus : |CPU CPU CPU|          |CPU CPU CPU|
 DMAC    :             |DMA DMA DMA|
 HOLD    : ____________|-----------|____________
 HLDA    : _____________|----------|____________
          idle cycle    active cycle   idle cycle
```
The states of the 8237: SI (idle), S0 (wait for HLDA), S1-S4 (transfer), SW (wait).

#### Disadvantages of DMA controllers
1. Extra hardware (DMA controller, bus arbitration logic) increases cost and complexity.
2. Programming the controller (address, count, mode) is more complex.
3. The CPU is stopped from using the bus during DMA (bus contention), so its throughput is reduced; in burst mode interrupts may be delayed.
4. Not efficient for small or slow transfers because of set-up overhead.
5. Memory and bus must be fast enough to support the DMA rate.
6. Errors or an erroneous address/count can overwrite memory and are hard to debug.
7. Cache coherence problems appear in systems with cache.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. During the DMA idle cycle, who owns the bus?
   A. The CPU, while the DMAC only samples DREQ lines
   B. The DMAC fully
   C. The memory
   D. The I/O device
   Answer: A. Idle cycle means no request, so CPU runs normally. (Key point: Idle cycle)

2. What starts the DMA active cycle?
   A. CPU sending DREQ
   B. DREQ, then HOLD and HLDA, after which the DMAC controls the buses
   C. Memory raising HLDA
   D. Interrupt return
   Answer: B. The sequence DREQ-HOLD-HLDA hands the bus to the DMAC. (Key point: Active cycle)

3. Why does DMA reduce CPU throughput?
   A. DMA makes the clock slower
   B. DMA erases the program
   C. The CPU cannot use the bus while the DMAC controls it
   D. DMA disables RAM
   Answer: C. Bus contention stalls the CPU during transfer. (Key point: Disadvantage: CPU)

4. Why is DMA inefficient for small or slow transfers?
   A. It has no address generation
   B. It cannot transfer fewer than 1 KB
   C. It needs no setup
   D. Set-up overhead outweighs the benefit
   Answer: D. Programming address, count and mode costs time. (Key point: Small transfers)

## Related in Instrumentation II

- [Case study: feasibility, drawbacks, convincing](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acs-2072kartik-feasibility) — Instrumentation II, chapter 10
- [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4
- [General process of creating a PCB](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apcb-creation-process) — Instrumentation II, chapter 8
- [Digital transmission system; analog vs digital](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aanalog-digital-transmission-compare) — Instrumentation II, chapter 5

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