--- title: "DMA concept; ROM/RAM interface at 4000H" subject: "Instrumentation II" chapter: 1 key: "semester_5/instrumentation_ii:dma-memory-interface-4000h" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dma-memory-interface-4000h site: BCT Engineering --- # DMA concept; ROM/RAM interface at 4000H Instrumentation II · Chapter 1: Microprocessor Based Instrumentation System - Asked in: 2069 Chaitra, 2+6 marks - Video: [8257 Direct Memory Access: Basics of DMA, HOLD, HLDA, and Working Mechanism](https://www.youtube.com/watch?v=XbyEsuYlXHQ) — Engineering Funda - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dma-memory-interface-4000h - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-1 ## Question Explain briefly the concept of DMA. Draw circuit Diagram of an interfacing circuit containing 4 KB ROM and 8 KB RAM. Assuming Base address in 4000H. You also need to draw write and read cycle timing diagram. ## Short answer DMA transfers data directly between I/O and memory using a controller that asserts HOLD, receives HLDA, and generates addresses. Memory interface: 4KB ROM at 4000H-4FFFH and 8KB RAM at 6000H-7FFFH decoded by 74LS138 with A15-A13; A12 gates ROM. Read/write timing: address in T1, RD/WR low in T2, data valid at T3. ## Answer #### Concept of DMA In **DMA** a DMA controller (8237) moves data between an I/O device and memory directly, without CPU instructions for each byte. The device asks with DREQ, the controller sends **HOLD**, the CPU gives the bus and answers **HLDA**, then the controller sends the address and MEMR'/MEMW', IOR'/IOW' signals and transfers bytes at high speed. It is used for block transfers like ADC data capture. #### Memory interface (8085, base address 4000H) - 4 KB ROM needs 12 address lines (A0-A11): ROM = **4000H-4FFFH**. - 8 KB RAM needs 13 address lines (A0-A12) and must start at a multiple of 2000H, so RAM = **6000H-7FFFH** (5000H-5FFFH is unused). | Chip | A15 A14 A13 A12 | Range | |---|---|---| | 4K ROM | 0 1 0 0 | 4000H-4FFFH | | 8K RAM | 0 1 1 x | 6000H-7FFFH | Decoder: 74LS138 with inputs C=A15, B=A14, A=A13, enables G1=1 (or IO/M' via G2B'), G2A'=0. Output Y2 (010) selects 4000H-5FFFH; Y3 (011) selects 6000H-7FFFH. ```text 8085 A0-A11 ------------------> ROM 4Kx8 (A0-A11) A0-A12 ------------------> RAM 8Kx8 (A0-A12) AD0-AD7 (via 74LS373 for low address; direct for data) ---> D0-D7 A15,A14,A13 -> [74LS138] Y2 --+ A12 ----------------------> [OR] --> ROM CS' Y3 -------------> RAM CS' RD' -> ROM OE', RAM OE' WR' -> RAM WE' IO/M' -> G2B' (enable decoder only for memory cycles) ``` ALE with a 74LS373 latch separates A0-A7 from AD0-AD7. #### Timing diagrams (8085 memory cycle, 3 T-states) ```text T1 T2 T3 CLK _|-|_|-|_|-|_|-|_|-|_ ALE __|--|______________ AD0-7 --< A0-A7 >< DATA >-- READ A8-15 -----< address >----- RD' -------\________/---- ``` ```text T1 T2 T3 ALE __|--|______________ AD0-7 --< A0-A7 >< DATA out> WRITE A8-15 -----< address >----- WR' -------\________/---- ``` In a read cycle the address is placed on the bus in T1, RD' goes low in T2 and the memory puts data on the bus, which the CPU latches at the rising edge of RD'. In a write cycle the CPU places data on AD0-AD7 and WR' low writes it into the RAM. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. With a 4 KB ROM at base 4000H, what is its address range? A. 4000H-4FFFH B. 4000H-7FFFH C. 4000H-40FFH D. 4000H-5FFFH Answer: A. 4 KB needs 12 address lines, so the range is 4000H to 4FFFH. (Key point: ROM address range) 2. Why does the 8 KB RAM start at 6000H and not 5000H? A. RAM must start after 7FFFH B. 8 KB must start at a multiple of 2000H, so 5000H is unusable C. 5000H is reserved for the CPU D. 8 KB RAM needs 14 address lines Answer: B. Alignment to 2000H gives 6000H-7FFFH, leaving 5000H-5FFFH unused. (Key point: RAM alignment) 3. How many address lines does 8 KB RAM need? A. 12 (A0-A11) B. 14 (A0-A13) C. 13 (A0-A12) D. 11 (A0-A10) Answer: C. 2^13 = 8192 bytes. (Key point: Lines needed) 4. In an 8085 read cycle, when does the CPU latch the data? A. At the falling edge of ALE B. At T1 start C. When WR' goes low D. At the rising edge of RD' Answer: D. RD' goes low in T2 and the data is latched as RD' rises. (Key point: Read cycle) ## Related in Instrumentation II - [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1 - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [MBI block diagram, advantages and DMA](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-block-advantages-dma) — Instrumentation II, chapter 1 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2 ## Related in other subjects - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4 - [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4 - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4