--- title: "DNL and INL errors in ADC and DAC" subject: "Instrumentation II" chapter: 4 key: "semester_5/instrumentation_ii:dnl-inl" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dnl-inl site: BCT Engineering --- # DNL and INL errors in ADC and DAC Instrumentation II · Chapter 4: Interfacing A/D And D/A Converters - Asked in: 2072 Chaitra, 2 marks; 2076 Asoj, 4 marks (asked 2 times) - Video: [ADC DC specifications: INL, DNL, Cin, leakage, Vref](https://www.youtube.com/watch?v=RQ9Vjp-8YEI) — Texas Instruments - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/dnl-inl - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-4 ## Question With necessary illustrations, explain the cause behind the DNL and INL errors in A/D and D/A conversion. ## Short answer DNL is the deviation of actual step width from 1 LSB due to resistor/switch mismatches and op‑amp offsets. INL is the cumulative DNL along the transfer curve, degrading accuracy. Major transitions worsen errors; DNL ≤ −1 LSB causes missing codes. ## Answer **Differential nonlinearity (DNL)** is the difference between the actual width of a code step (ADC) or the actual output step (DAC) and the ideal width of 1 LSB. **Integral nonlinearity (INL)** is the maximum deviation of the actual transfer curve from the ideal straight line (end-point or best fit). INL is the accumulation of the DNL errors: INL(k) = sum of DNL up to code k. #### DAC illustration ```text Output ^ ideal line | * / | * / * actual outputs | * / INL = deviation from line | * / | * / DNL = step height - 1 LSB | * / +--------------------> Digital code ``` #### ADC illustration (staircase) ```text Code ^ ____ 3 | ___| wide step : DNL > 0 2 | __| 1 || narrow step : DNL < 0 ; width 0 = missing code (DNL = -1) 0 +---------------> Analog input ``` #### Causes 1. **Resistor mismatch** in the R-2R ladder or weighted resistor network: errors in the weights, especially the MSB resistors, give large errors at major transitions (for example 0111 1111 to 1000 0000). 2. **Switch on-resistance and leakage** differing from bit to bit. 3. **Comparator offsets and threshold errors** in flash and SAR ADCs; unequal reference ladder resistors. 4. **Reference voltage and op-amp errors:** non-linear reference, op-amp gain and offset. 5. **Capacitor mismatch** in capacitive DAC / SAR ADC. 6. **Temperature and supply variation,** noise, finite settling and timing errors. #### Consequences - DNL <= -1 LSB: **missing codes** (ADC) or **non-monotonic** output (DAC). DNL must be within +/-1 LSB for guaranteed monotonicity. - INL: the overall accuracy is reduced by the INL value; for 12-bit with INL = +/-2 LSB the accuracy is only about 10 bits. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. INL is? A. Step width error B. Offset C. Max deviation from ideal straight line D. Noise Answer: C. Overall curve deviation. (Key point: Definition) 2. Relation between INL and DNL? A. Equal B. Independent C. INL accumulates DNL D. INL is smaller Answer: C. Sum of DNL up to code k. (Key point: Relation) 3. Major cause in R-2R DAC? A. Cable B. Display C. Clock D. Resistor mismatch esp. MSB Answer: D. MSB weights errors. (Key point: Cause) 4. DNL range for monotonic? A. 0 only B. Within +/-1 LSB C. Above 2 D. +/-10 Answer: B. Guaranteed within +/-1 LSB. (Key point: Monotonic) ## Related in Instrumentation II - [Errors in ADC and DAC](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-dac-errors) — Instrumentation II, chapter 4, asked 7× - [Characteristics of ADC and DAC](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-dac-characteristics) — Instrumentation II, chapter 4, asked 2× - [Mitigating DNL and harmonic distortion errors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adnl-harmonic-distortion) — Instrumentation II, chapter 4 - [Static and dynamic errors in DAC](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adac-static-dynamic-errors) — Instrumentation II, chapter 4 - [ADC at 80H with 8255A: display on port B LEDs](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-8255-80h-leds) — Instrumentation II, chapter 2 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 ## Related in other subjects - [Counter-type ADC numerical (VFS = 12 V)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acounter-adc-12v-numerical) — Advanced Electronics, chapter 3 - [Dual slope ADC block diagram; integral linearity](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Adual-slope-integral-linearity) — Advanced Electronics, chapter 3 - [Count-up ADC numerical (VFS = 16 V)](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Acount-up-adc-16v-numerical) — Advanced Electronics, chapter 3 - [R-2R ladder DAC versus weighted resistor](https://www.bctengineer.com/question.md?key=semester_4%2Finstrumentation_i%3Ar-2r-ladder-dac) — Instrumentation I, chapter 5