--- title: "Double handshake data transfer with 8255-PPI" subject: "Instrumentation II" chapter: 2 key: "semester_5/instrumentation_ii:double-handshake-8255" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/double-handshake-8255 site: BCT Engineering --- # Double handshake data transfer with 8255-PPI Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System - Asked in: 2072 Kartik, 5 marks - Video: [Input and Output Using Handshake Signals](https://www.youtube.com/watch?v=1QGcl8NDxCQ) — TutorialsPoint - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/double-handshake-8255 - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2 ## Question Consider a double handshake scheme that allows data transfer from an input peripheral device to an 8085-microprocessor through an 8255-PPI. (i) List all control signals that get exchanged between the devices. (ii) Draw a detailed timing diagram showing the exchange of control and data signals. Include the cause and effect arrows in your timing diagram. (iii) With a neat sketch show the overall system diagram between the modules mentioned above. (iv) Generate an appropriate control word based upon your drawing and derive the address of the control register of the 8255-PPI used in your design. ## Short answer 8255 port A mode 1 input: STB' (PC4) latches data, IBF (PC5) goes high, INTR (PC3) interrupts CPU. Control word B0H, INTE set by BSR 09H. Base address 80H, control register 83H. ## Answer In the double handshake method, each data transfer needs two signals in each direction: the peripheral says "data is ready" and the interface says "data was received". We use the 8255 port A in **mode 1 (strobed input)**. #### (i) Control signals - From the peripheral: **STB'** (strobe, data valid), 8-bit data on PA0-PA7. - From the 8255: **IBF** (input buffer full, acknowledge to the peripheral), **INTR** (interrupt request to 8085, PC3), controlled by **INTE**. - From the 8085: **RD'**, CS', A0, A1 and RESET. #### (ii) Timing diagram with cause and effect ```text Data ---< valid >---------------------------- STB' -----\_______/-------------------------- IBF ____________/----------------\_________ INTR ________________/-----------\__________ RD' ---------------------\____/------------- (1) STB' low -> data latched (2) STB' low -> IBF high (peripheral told: wait) (3) STB' rising (and INTE=1) -> INTR high (4) 8085 ISR: RD' low -> INTR low (5) RD' rising -> IBF low (peripheral can send next byte) ``` #### (iii) System diagram ```text Peripheral 8255 8085 D0-D7 ------------> PA0-PA7 D0-D7 <----> AD0-AD7 STB' ------------> PC4 RD',WR' IBF <------------ PC5 CS',A0,A1 <- decoder, A0,A1 PC3 INTR ---------> RST 5.5 (INTR input) ``` #### (iv) Control word and address Assume I/O mapped 8255 with base address 80H (A7 = 1 selects it, A1A0 select register): Port A = 80H, B = 81H, C = 82H, control = **83H**. Control word: D7=1; D6D5 = 01 (port A mode 1); D4 = 1 (A input); D3 = 0 (PC6, PC7 output); D2 = 0 (port B mode 0); D1 = 0 (B output); D0 = 0 (C lower output) = 1011 0000 = **B0H**. Enable INTE_A by BSR of PC4: control word 0000 1001 = **09H**. ```text MVI A,B0H OUT 83H MVI A,09H OUT 83H ; INTE A = 1 EI ``` The ISR executes IN 80H to get the data. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What do the two signals in a double handshake mean? A. CPU says read (RD'); CPU says write (WR') B. Interface says reset; peripheral says clock C. Both only indicate power is on D. Peripheral says data is ready (STB'); interface says data was received (IBF) Answer: D. Each transfer has a request from the sender and an acknowledgement from the receiver. (Key point: Handshake meaning) 2. Which 8255 mode is used for the strobed input double handshake? A. Mode 0 of port A B. Mode 2 of port B C. Mode 1 (strobed input) of port A D. BSR mode only Answer: C. Mode 1 provides STB', IBF and INTR for handshake input. (Key point: Mode) 3. In the timing sequence, what makes IBF go low so the peripheral may send the next byte? A. The falling edge of STB' B. The rising edge of INTR C. The rising edge of RD' from the 8085 D. The reset of the 8255 Answer: C. After the CPU reads the data, RD' going high clears IBF. (Key point: Cause and effect) 4. What is the mode-set control word for port A mode 1 input, B mode 0 output, C lower output, PC6-7 output? A. A0H B. B0H C. 90H D. B4H Answer: B. 1 01 1 0 0 0 0 = 1011 0000 = B0H. (Key point: Control word) ## Related in Instrumentation II - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [ADC with 8085 using 8255: fan and heater control](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-8255-fan-heater) — Instrumentation II, chapter 4 - [8255 at A0A0H: interface and control words](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-a0a0h-control-words) — Instrumentation II, chapter 2 - [Technical benefits of 8255 PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-benefits) — Instrumentation II, chapter 2, asked 2× - [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2 ## Related in other subjects - [8085 ALP: transfer data with more than 3 ones](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-ones-greater-than-3) — Microprocessor, chapter 2 - [Characteristics and signals of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-characteristics-signals) — Microprocessor, chapter 2 - [Timing diagram of STA 8050H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Atiming-sta-8050h) — Microprocessor, chapter 2 - [Slew-rate check for four input signals](https://www.bctengineer.com/question.md?key=semester_4%2Fadvanced_electronics%3Aslew-rate-multiple-signals) — Advanced Electronics, chapter 2