---
title: "Full vs partial address decoding for memory"
subject: "Instrumentation II"
chapter: 2
key: "semester_5/instrumentation_ii:full-vs-partial-decoding"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/full-vs-partial-decoding
site: BCT Engineering
---

# Full vs partial address decoding for memory

Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System

- Asked in: 2075 Chaitra, 4 marks
- Video: [Address decoding Circuit](https://www.youtube.com/watch?v=esqh_3qi-R4) — IOE-BCT
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/full-vs-partial-decoding
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2

## Question

Among full or partial address decoding, which method of address decoding do you choose while interfacing memory device? Give reasons with suitable example.

## Short answer

Full address decoding is preferred because it gives each memory location a unique address, eliminates foldback images, and uses address space efficiently for expansion. For example, a 2K RAM at 0000H–07FFH decodes all upper address lines A15–A11 to select the chip only in that range.

## Answer

For interfacing memory I choose **full (absolute, unique) address decoding**.

#### Reasons
1. **Unique address:** each location has exactly one address, so there is no ambiguity and no bus conflict when memories are expanded.
2. **Efficient use of address space:** no image (foldback) addresses are wasted, so the maximum memory can be added later.
3. **Easy expansion and relocation:** new chips can be placed in free blocks without conflicts.
4. **Simple software:** programs and monitor routines use exactly one address map. This is needed for ROM at the reset vector and for operating systems.
5. Partial decoding saves a few gates, but the saving is small in a memory system.

#### Example (8085, 2K x 8 RAM at 0000H-07FFH)
The chip has 11 address lines (A0-A10). The remaining lines A15-A11 are used to generate CS'.
- **Full decoding:** CS' = A15 + A14 + A13 + A12 + A11 + IO/M (a 6-input OR gate). CS' is low only when all these inputs are 0, so the chip responds only at 0000H-07FFH.
- **Partial decoding:** CS' = A15 only (low when A15 = 0). The chip responds at 0000H-07FFH, 0800H-0FFFH, ... 7800H-7FFFH (16 images), so the region 0800H-7FFFH cannot be used for other devices.

```text
 A15..A11, IO/M --[6-input OR]--> CS'    A10..A0 --> chip A10..A0
 RD' -> OE'  WR' -> WE'
```
Partial decoding is acceptable only for very small systems or I/O ports where only a few devices exist.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which decoding does the answer choose for memory interfacing?
   A. Partial decoding
   B. Full (absolute) decoding
   C. No decoding
   D. Linear select only
   Answer: B. Full decoding gives each location exactly one address, avoiding conflicts and wasted space. (Key point: Decoding choice)

2. What is the main drawback of partial decoding in the 2K RAM example?
   A. The RAM cannot be read
   B. Chip responds at many image addresses, blocking the range for other devices
   C. It needs more address lines on the chip
   D. It stops RD' working
   Answer: B. Using only NOT A15 makes the chip respond at 16 images, so 0800H-7FFFH cannot be used by others. (Key point: Image addresses)

3. For a 2K x 8 RAM at 0000H-07FFH, which lines are decoded for full decoding?
   A. A15-A11 (plus IO/M')
   B. A10-A0
   C. A15 only
   D. A7-A0
   Answer: A. A0-A10 go to the chip; A15-A11 are decoded for CS' so it responds only at 0000H-07FFH. (Key point: Full decoding of 2K RAM)

## Related in Instrumentation II

- [Unique vs non-unique address decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aunique-vs-nonunique-decoding) — Instrumentation II, chapter 2
- [PC interfacing techniques for I/O device](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apc-interfacing-techniques) — Instrumentation II, chapter 2, asked 2×
- [8086 RAM/EPROM interfacing with reset address](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arom-ram-8086-fffffh) — Instrumentation II, chapter 1
- [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2
- [I/O mapped vs memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aiomapped-vs-memmapped) — Instrumentation II, chapter 2
- [USB 1.1 vs 2.0 and device identification](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb11-vs-usb20-identify) — Instrumentation II, chapter 3

## Related in other subjects

- [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4
- [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4
- [Address decoding for two 8 KB RAM at C000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8kb-ram-c000h) — Microprocessor, chapter 4