---
title: "Problems due to impedance mismatch"
subject: "Instrumentation II"
chapter: 7
key: "semester_5/instrumentation_ii:impedance-mismatch-problems"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/impedance-mismatch-problems
site: BCT Engineering
---

# Problems due to impedance mismatch

Instrumentation II · Chapter 7: Circuit Design

- Asked in: 2075 Asoj, 2 marks
- Video: [Impedance Matching Basics](https://www.youtube.com/watch?v=XCiBvhleDIM) — All Electronics Channel
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/impedance-mismatch-problems
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-7

## Question

What are the problems due to impedance mismatch?

## Short answer

Impedance mismatch causes signal reflections, leading to ringing, overshoot, and undershoot that can cause false triggering. It also results in signal distortion, increased settling time, reduced power transfer, and higher EMI/crosstalk.

## Answer

When source, line and load impedances are not equal, the problems are:
1. **Signal reflections** from the load/discontinuity back toward the source (Γ = (Z_L - Z₀)/(Z_L + Z₀)).
2. **Ringing, overshoot and undershoot** on edges; can exceed the device ratings or cause false triggering.
3. **Signal distortion and degraded signal integrity**, with false logic levels and data errors.
4. **Increased delay and timing errors** (settling time), and reduced maximum speed.
5. **Loss of power transfer** to the load (reduced amplitude).
6. **Higher EMI/crosstalk** radiation from the reflected energy.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the main problem when source, line and load impedances are unequal?
   A. Signal reflections back toward the source
   B. Higher supply voltage
   C. Faster propagation
   D. Lower noise
   Answer: A. Part of the wave reflects, given by Γ = (Z_L - Z0)/(Z_L + Z0). (Key point: Reflections)

2. How can ringing, overshoot and undershoot harm a circuit?
   A. They reduce EMI
   B. They can exceed device ratings or cause false triggering
   C. They speed up edges beneficially
   D. They have no effect on logic levels
   Answer: B. Excursions can damage inputs or cause false logic transitions and data errors. (Key point: Ringing consequences)

3. How does mismatch affect timing?
   A. It shortens settling time
   B. It removes delay
   C. It increases delay and settling time, reducing maximum speed
   D. It only changes colour of signals
   Answer: C. Reflections need time to die out, causing timing errors and limiting speed. (Key point: Timing effect)

## Related in Instrumentation II

- [Stub discontinuity and crosstalk causes](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Astub-discontinuity-crosstalk) — Instrumentation II, chapter 7

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