--- title: "Interrupt driven data transfer" subject: "Instrumentation II" chapter: 1 key: "semester_5/instrumentation_ii:interrupt-driven-transfer" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/interrupt-driven-transfer site: BCT Engineering --- # Interrupt driven data transfer Instrumentation II · Chapter 1: Microprocessor Based Instrumentation System - Asked in: 2073 Chaitra, 3 marks; 2075 Asoj, 1+5 marks (asked 2 times) - Video: [Interrupt Driven I/O: Structure and Data Transfer Process Explained | COA](https://www.youtube.com/watch?v=iuOjtZlix4E) — Engineering Funda - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/interrupt-driven-transfer - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-1 ## Question Explain the interrupt driven data transfer scheme with the flowchart of the interrupt subroutine and main program sequence. ## Short answer Interrupt-driven I/O allows the CPU to execute its main program until a peripheral signals readiness via an interrupt request. The CPU saves context, vectors to an ISR, transfers one data byte, updates pointer/counter, clears the interrupt, and returns, maximizing CPU utilization for slow devices. ## Answer In interrupt driven I/O, the peripheral informs the processor when it is ready by activating an interrupt request line. The processor works on its main program and transfers data only when interrupted, so no time is wasted in polling. #### Sequence 1. Main program initialises the port, loads pointers/counter, and enables interrupts (EI). 2. The device becomes ready and sets INTR. 3. The CPU finishes the current instruction, checks the request (and mask), and sends INTA'. 4. The return address (PC) and flags are pushed on the stack; the PC is loaded with the ISR address (vector). 5. The ISR saves registers, reads or writes the byte (IN/OUT), updates pointer and counter, clears the request, restores registers, enables interrupts, and executes RET/IRET. 6. The main program continues from where it stopped. #### Flowcharts ```text Main program Interrupt service routine +----------+ +-------------------+ | Start | | Save registers | +----+-----+ +---------+---------+ +----v-----+ +---------v---------+ | Initialise| | Read/write data | | port, EI | | via port | +----+-----+ +---------+---------+ +----v-----+ +---------v---------+ | Do other |<- INTR | Update pointer, | | tasks | occurs | counter | +----+-----+ +---------+---------+ | +---------v---------+ v | Restore registers | (continue) | EI, RET | +-------------------+ ``` #### 8085 skeleton ```text MVI A,0BH ; SIM: enable RST 7.5 SIM EI LOOP: ... ; main work JMP LOOP ISR: PUSH PSW IN 80H ; read data STA 2000H POP PSW EI RET ``` Advantage: efficient CPU use. Disadvantage: interrupt latency and overhead per byte, so not suitable for very fast block transfers (use DMA). ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why does interrupt driven I/O save CPU time? A. The CPU works on the main program and transfers data only when the device interrupts B. The CPU checks the status flag continuously C. The DMA controller does all transfers D. The device waits for the CPU forever Answer: A. No polling loop is needed; the device signals when ready. (Key point: Benefit over polling) 2. What does the CPU do after INTR before running the ISR? A. Aborts the current instruction and clears the stack B. Finishes the current instruction, sends INTA', and pushes the return address and flags C. Resets all registers to zero D. Waits for DREQ from the DMAC Answer: B. The CPU completes the instruction, acknowledges, saves the PC, then jumps to the ISR. (Key point: Response to interrupt) 3. Which is a correct ISR sequence? A. Return first, then transfer the byte B. Reset the processor, then transfer C. Save registers, transfer byte, update pointer and counter, restore registers, enable interrupts, return D. Disable the device and never return Answer: C. The ISR preserves context, services the device, and returns with EI and RET. (Key point: ISR actions) ## Related in Instrumentation II - [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2 - [ADC804 with 8255 control word and program](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc804-8255-program) — Instrumentation II, chapter 4 - [Interfacing 8-bit ADC using interrupt](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc-interrupt-interface) — Instrumentation II, chapter 4, asked 2× - [Data transfer techniques for slow I/O](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-speed-mismatch) — Instrumentation II, chapter 1, asked 3× - [Basic data transfer mechanisms in USB](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-transfer-mechanisms) — Instrumentation II, chapter 3 - [USB standards and data transfer mechanisms](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-standards-transfer-mech) — Instrumentation II, chapter 3 ## Related in other subjects - [Interrupt-driven I/O with vectored interrupt](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avectored-interrupt-io-flow) — Embedded System, chapter 5, asked 3× - [Programmed vs interrupt-driven vs DMA](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aio-techniques-compare) — Computer Organization and Architecture, chapter 7, asked 5× - [DMA vs programmed and interrupt-driven I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-overcomes) — Computer Organization and Architecture, chapter 7, asked 3× - [Sequence of steps when interrupt occurs](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterrupt-occurrence-steps) — Microprocessor, chapter 5, asked 2×