---
title: "Data transfer techniques for slow I/O"
subject: "Instrumentation II"
chapter: 1
key: "semester_5/instrumentation_ii:io-speed-mismatch"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/io-speed-mismatch
site: BCT Engineering
---

# Data transfer techniques for slow I/O

Instrumentation II · Chapter 1: Microprocessor Based Instrumentation System

- Asked in: 2074 Asoj, 6 marks; 2076 Chaitra, 5 marks; 2068 Baisakh (old course), 8 marks (asked 3 times)
- Video: [DATA TRANSFER TECHNIQUES OF 8085|| CONCEPT OF NEED DATA TRANSFER Technique](https://www.youtube.com/watch?v=Vh9QcyXSCRc) — Education-The Right Away-By Preeti Chhabra
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/io-speed-mismatch
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-1

## Question

If the speeds of I/O devices do not match the speed of the microprocessor, what types of data transfer techniques are used? Describe them with necessary block diagrams and control signals.

## Short answer

When I/O speed mismatches, use: status check (polling with handshake, CPU wastes time), interrupt-driven transfer (device signals readiness via INTR, CPU performs ISR to transfer byte, allowing concurrency), or direct memory access (DMA controller takes bus control from CPU, transfers block directly between device and memory). DMA offers highest speed with lowest CPU load.

## Answer

When the I/O device is much slower than the microprocessor (or has an unpredictable timing), the processor must **synchronise** with it. The techniques are: (1) status check (polling) with handshake, (2) interrupt driven transfer, and (3) DMA.

#### 1. Handshake / status check (programmed I/O)
The processor reads a status flag of the device repeatedly until it is ready, then transfers data. Control signals (for an input device with an 8255 in mode 1): **STB'** (strobe from device: data is valid), **IBF** (input buffer full: tells the device data is latched), and for output **OBF'** and **ACK'**.

```text
 Device                 Port (8255)            CPU
   | --- data ---------> |                      |
   | --- STB'  --------> | IBF = 1 ------------>| polls status
   | <-- IBF   --------- |                      | IN data
   |                     | IBF = 0 (after RD')  |
```
Simple, but the CPU wastes time in the polling loop.

#### 2. Interrupt driven transfer
The device raises an interrupt request (INTR/IRQ) when it is ready. The CPU completes the current instruction, saves the return address, and jumps to the service routine (via INTA' and vector), which transfers the byte and returns. The CPU does other work meanwhile.

```text
 Device --INTR--> [Interrupt controller] --INT--> CPU
 CPU --INTA'--> controller (vector)      CPU <-> Data bus <-> Device
```
Signals: INTR/INT, INTA', RD', WR', IR0-IR7.

#### 3. DMA (direct memory access)
For fast or block transfers, a DMA controller (8237) takes over the bus. The device sends **DREQ**, the controller sends **HOLD** to the CPU, the CPU answers **HLDA** and floats its buses, the controller issues **DACK** to the device, and generates address, MEMR'/IOW' (or MEMW'/IOR') for each byte until the count is over.

```text
 Device --DREQ--> DMAC --HOLD--> CPU
 Device <--DACK-- DMAC <--HLDA-- CPU
 DMAC drives address bus, MEMR', MEMW', IOR', IOW'
 Data goes Device <-> Memory directly
```

| Technique | CPU load | Speed | Hardware |
|---|---|---|---|
| Polling | Very high | Low | Very simple |
| Interrupt | Medium | Medium | Interrupt controller |
| DMA | Very low | Highest | DMA controller |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When an I/O device is much slower than the microprocessor or has unpredictable timing, what must be done?
   A. The processor must synchronise with the device using polling, interrupt or DMA transfer
   B. The device clock must be raised to the CPU speed
   C. The CPU must stop and wait until the program ends
   D. Data must be sent without any control signals
   Answer: A. Mismatched speeds are handled by synchronisation techniques: status check, interrupt-driven and DMA. (Key point: Need to synchronise)

2. In 8255 mode 1 input handshake, what does IBF indicate?
   A. The device has finished sending all data
   B. The input buffer is full: data has been latched and the CPU can read it
   C. The CPU has acknowledged an interrupt
   D. The output buffer is empty
   Answer: B. STB' from the device latches the data and IBF goes high; it falls after the CPU reads. (Key point: 8255 mode 1 handshake)

3. Which is the correct order of signals in a DMA transfer?
   A. HLDA from CPU, DREQ, HOLD, DACK
   B. HOLD from device, DACK from CPU, DREQ, HLDA
   C. DREQ from device, HOLD to CPU, HLDA from CPU, DACK to device
   D. INTR, INTA', HOLD, DREQ
   Answer: C. The device requests with DREQ, the DMAC asks the CPU with HOLD, the CPU replies HLDA and DACK goes to the device. (Key point: DMA sequence)

4. Which technique gives the lowest CPU load and highest speed for block transfers?
   A. Polling
   B. Interrupt driven transfer
   C. Handshake status check
   D. DMA
   Answer: D. DMA moves data directly between device and memory, so CPU load is very low and speed is highest. (Key point: Comparison of techniques)

## Related in Instrumentation II

- [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2
- [Parallel transfer schemes and 8255A block diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aparallel-transfer-8255-block) — Instrumentation II, chapter 2
- [Basic data transfer mechanisms in USB](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-transfer-mechanisms) — Instrumentation II, chapter 3
- [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6×
- [Rationale for microprocessor; open-loop MBI; DMA](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arationale-open-loop-dma) — Instrumentation II, chapter 1
- [Compact data logger characteristics and block diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acompact-dl-block) — Instrumentation II, chapter 5

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- [Time and space mean speed from 20 spot speeds](https://www.bctengineer.com/question.md?key=semester_7%2Ftransportation_engineering_ii%3Aspot-speed-20-observations-travel-time) — Transportation Engineering II, chapter 1