---
title: "I/O mapped vs memory mapped I/O"
subject: "Instrumentation II"
chapter: 2
key: "semester_5/instrumentation_ii:iomapped-vs-memmapped"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/iomapped-vs-memmapped
site: BCT Engineering
---

# I/O mapped vs memory mapped I/O

Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System

- Asked in: 2074 Chaitra, 5 marks
- Video: [Memory Mapped IO vs IO Mapped IO in 8085 Microprocessor: Key Differences Explained](https://www.youtube.com/watch?v=iDzdyRCdqnA) — Engineering Funda
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/iomapped-vs-memmapped
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2

## Question

Differentiate I/O mapped I/O and memory mapped I/O with suitable examples. How can you generate I/O mapped and memory mapped signals using IO/M, RD and WR signals?

## Short answer

I/O-mapped I/O uses separate port addresses and IN/OUT instructions, while memory-mapped I/O shares the memory space and uses all memory instructions like MOV and STA. In 8085, MEMR' and MEMW' are generated by gating RD' and WR' with IO/M low; IOR' and IOW' by gating with IO/M high.

## Answer

| Point | I/O mapped I/O | Memory mapped I/O |
|---|---|---|
| Address space | Separate 8-bit (256 ports) in 8085; 16-bit in 8086 | Shares memory space |
| Address bits | 8 bits (A0-A7) | 16 bits (A0-A15) |
| Instructions | Only IN, OUT (accumulator) | All memory instructions (MOV, ADD, LDA, STA) |
| Control signals | IO/M = 1, IOR', IOW' | IO/M = 0, MEMR', MEMW' |
| Memory available | Full memory for RAM/ROM | Reduced by ports |
| Speed | Slower for data processing | Faster, can operate on data directly |
| Decoding | Simple (8 bits) | More hardware (16 bits) |
| Example | IN 80H / OUT 81H | LDA 8000H / STA 9000H |

#### Generation of control signals (8085)
The 8085 gives RD', WR' and IO/M (high = I/O, low = memory). Combine them with gates:
```text
 MEMR' = RD' OR IO/M        (low only when RD'=0 and IO/M=0)
 MEMW' = WR' OR IO/M
 IOR'  = RD' OR (NOT IO/M)  (low only when RD'=0 and IO/M=1)
 IOW'  = WR' OR (NOT IO/M)
```
```text
 RD' ----+--[OR]---- MEMR'      RD' ---[OR]---- IOR'
 IO/M ---+                      IO/M -[NOT]--+
```
These signals then enable memory chips (MEMR', MEMW') or port devices (IOR', IOW'). A 3-to-8 decoder (74LS138) can be used with IO/M on an enable input.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which instructions access I/O mapped ports in the 8085?
   A. Only IN and OUT
   B. LDA and STA
   C. MOV and ADD
   D. Any memory instruction
   Answer: A. I/O mapped I/O uses IN/OUT with the accumulator. (Key point: Instructions)

2. How many ports can the 8085 address using I/O mapped I/O?
   A. 256 using 8-bit addresses
   B. 64K using 16-bit addresses
   C. 16 ports
   D. 1024 ports
   Answer: A. 8 bits give 256 ports. (Key point: Address size)

3. How is MEMR' produced from RD' and IO/M?
   A. MEMR' = RD' OR IO/M, low only when RD'=0 and IO/M=0
   B. MEMR' = RD' AND IO/M
   C. MEMR' = RD' OR NOT IO/M
   D. MEMR' = WR' OR IO/M
   Answer: A. OR gate gives low only when both are low. (Key point: MEMR' generation)

4. How is IOR' generated?
   A. IOR' = RD' OR IO/M
   B. IOR' = RD' OR (NOT IO/M)
   C. IOR' = WR' OR IO/M
   D. IOR' = RD' AND IO/M
   Answer: B. IO/M must be 1 for I/O, so it is inverted before the OR. (Key point: IOR' generation)

5. What is the effect on memory in memory mapped I/O?
   A. Memory is increased
   B. No effect
   C. Reduced available memory because ports share the space
   D. Memory is doubled
   Answer: C. Ports occupy memory addresses. (Key point: Memory available)

## Related in Instrumentation II

- [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2
- [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2
- [Ice cream factory MBI with 8255 at 5000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aicecream-ppi-5000h) — Instrumentation II, chapter 2
- [PC based concrete purifying factory with 8255](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aconcrete-purifying-ppi-4000h) — Instrumentation II, chapter 2

## Related in other subjects

- [Uses of ALE, IO/M, READY, RD pins](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-pin-uses-ale-iom) — Microprocessor, chapter 2
- [Isolated I/O vs memory-mapped I/O](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aisolated-vs-mmio) — Computer Organization and Architecture, chapter 7, asked 2×
- [Arbitration and memory-mapped vs standard I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aarbitration-memory-mapped-io) — Embedded System, chapter 5
- [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4