---
title: "Low power design reasons and guidelines"
subject: "Instrumentation II"
chapter: 7
key: "semester_5/instrumentation_ii:low-power-guidelines"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/low-power-guidelines
site: BCT Engineering
---

# Low power design reasons and guidelines

Instrumentation II · Chapter 7: Circuit Design

- Asked in: 2073 Chaitra, 5 marks; 2071 Shrawan, 2 marks; 2069 Chaitra, 2+4 marks (asked 3 times)
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/low-power-guidelines
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-7

## Question

What are the reasons for using low power design? Explain the guidelines for low power design.

## Short answer

Low power design extends battery life, reduces heat and cost, and improves reliability. Guidelines: use lowest feasible supply voltage and clock frequency, sleep modes, low-power components, minimize switched capacitance, avoid static current paths, and use efficient DC-DC converters.

## Answer

#### Reasons for low power design
1. **Battery life:** portable and handheld devices (phones, sensors, wearables) need to run for a long time on small batteries.
2. **Heat reduction:** less power means less heating, so smaller heat sinks, no fans, smaller size and better reliability (failure rate rises with temperature).
3. **Lower cost** of supplies, batteries and cooling; lower running energy cost.
4. **Reliability and noise:** low current gives less supply noise and less EMI.
5. **Environment and regulation:** energy-saving standards, remote or solar-powered systems.
6. **Packaging density:** more circuits in smaller packages.

#### Guidelines
1. **Use a low supply voltage:** CMOS dynamic power P = C·V²·f falls with the square of V, so use 3.3 V or 1.8 V devices.
2. **Reduce the clock frequency** to the lowest value that meets the speed need; use clock gating.
3. **Use sleep/idle/power-down modes** and wake only on events/interrupts; shut off unused peripherals.
4. **Choose low-power components:** CMOS logic, low-power MCU, low-quiescent-current regulators (LDO or efficient switching regulators), micro-power op-amps.
5. **Minimise the capacitance** being switched: short traces, fewer loads, reduce the activity of nodes (fewer toggles).
6. **Avoid static current:** no pull-up resistors left conducting, high-value resistors where possible, unused inputs tied to defined levels (floating CMOS inputs draw current).
7. **Power budget:** compute the current of each block and duty cycle; use duty cycling for sensors and radios.
8. **Efficient power conversion:** use high-efficiency DC-DC converters instead of linear regulators when the voltage drop is large.
9. **Use software techniques:** efficient algorithms, interrupt-driven rather than polling code.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which expression gives CMOS dynamic power?
   A. P = C V f
   B. P = V/R only
   C. P = C V^2 f
   D. P = L I^2
   Answer: C. It depends on the square of voltage, so lowering V saves most. (Key point: Dynamic power)

2. Why use a lower supply voltage?
   A. Power is independent of V
   B. Dynamic power falls with the square of V
   C. It raises clock speed
   D. It increases static current
   Answer: B. Halving V cuts dynamic power to a quarter. (Key point: Supply voltage)

3. Which technique reduces average power?
   A. Sleep/power-down modes, waking on interrupts
   B. Polling continuously
   C. Leaving peripherals on
   D. Floating CMOS inputs
   Answer: A. Interrupt-driven wake-up avoids wasted active time. (Key point: Sleep modes)

4. Why tie unused CMOS inputs to a defined level?
   A. They raise the clock
   B. They need pull-ups to dissipate heat
   C. They lower noise
   D. Floating inputs draw excess current
   Answer: D. A floating CMOS input can sit mid-rail and turn both transistors partly on. (Key point: Floating inputs)

## Related in Instrumentation II

- [High speed circuit design guidelines](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ahigh-speed-guidelines) — Instrumentation II, chapter 7, asked 3×

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