--- title: "Memory-mapped I/O design for 8085" subject: "Instrumentation II" chapter: 2 key: "semester_5/instrumentation_ii:memmapped-io-design-1000h" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/memmapped-io-design-1000h site: BCT Engineering --- # Memory-mapped I/O design for 8085 Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System - Asked in: 2072 Kartik, 4 marks - Video: [U1 L29 | Memory Mapped I/O Interfacing | Interfacing in 8085 Microprocessor](https://www.youtube.com/watch?v=yi2-SgbcAoc) — Techno Tutorials ( e-Learning) - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/memmapped-io-design-1000h - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2 ## Question What benefit are obtained from a memory-mapped I/O design? Design an interface arrangement for 8085 microprocessor to map output ports in address space 1000H to 2000H and input ports in address space 3000H to 4000H. ## Short answer Memory-mapped I/O allows all memory instructions to access ports, supports up to 64K ports, and uses no separate I/O signals. For output block 1000H-1FFFH, decode A15-A12=0001 with MEMW'; for input block 3000H-3FFFH, decode 0011 with MEMR'. Use 74LS138 with A15,A13,A12 as inputs, A14 and IO/M as enables. ## Answer #### Benefits of memory mapped I/O 1. All memory reference instructions (LDA, STA, MOV M,A, ADD M, ANA M) can access ports, so data in ports can be processed directly without moving it to the accumulator. 2. A large number of I/O ports is possible (up to 64K addresses) and all addressing modes are available. 3. No separate I/O control signals (IOR', IOW') or special IN/OUT instructions are needed; ports use the same control signals as memory. 4. Disadvantage: ports use up memory addresses and decoding needs the full 16-bit address. #### Design Assumption: output ports occupy the block 1000H-1FFFH and input ports the block 3000H-3FFFH (the end addresses 2000H and 4000H are taken as the beginning of the next blocks, because the given ranges can be selected exactly only in 4K blocks using A15-A12). | Block | A15 A14 A13 A12 | Range | Signal | |---|---|---|---| | Output ports | 0 0 0 1 | 1000H-1FFFH | MEMW' | | Input ports | 0 0 1 1 | 3000H-3FFFH | MEMR' | Use a 74LS138 with inputs C = A15, B = A13, A = A12, and A14 on the enable G2A'. Enables: G1 = 1, G2A' = A14, G2B' = IO/M (so the decoder works only for memory cycles with A14 = 0). Output Y1 (A13 A12 = 01) -> output block; Y3 (A13 A12 = 11) -> input block. Output port select = Y1' OR WR'; this goes low during the write pulse and rises at its end, so it can clock a 74LS374 output latch. Input port select = Y3' OR RD', which enables a tri-state buffer (74LS244). ```text A15 -> C A13 -> B A12 -> A A14 -> G2A' IO/M -> G2B' +5V -> G1 Y1' --[OR]-- WR' --> clock of 74LS374 latch : output port (D0-D7 in) Y3' --[OR]-- RD' --> enable of 74LS244 buffer : input port (D0-D7 out) AD0-AD7 (after demultiplexing) are connected to the port data lines ``` Individual ports within each block are chosen using lower address lines (A0-A2), for example by another decoder. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which is a benefit of memory-mapped I/O? A. It needs fewer address lines for decoding B. It saves memory addresses C. It uses faster IN and OUT instructions only D. Memory instructions such as ADD M or ANA M can work directly on port data Answer: D. Ports are accessed like memory, so all memory-reference instructions and addressing modes can be used. (Key point: Benefit) 2. What is a disadvantage of memory-mapped I/O? A. It cannot access more than 256 ports B. It needs special IN/OUT instructions C. Ports use up memory addresses and the full 16-bit address must be decoded D. It cannot use the accumulator Answer: C. Port addresses reduce the memory space available and require full 16-bit decoding. (Key point: Disadvantage) 3. In the design, which A15-A12 pattern selects the output port block 1000H-1FFFH? A. 0011 B. 0010 C. 0001 D. 1000 Answer: C. 1000H = 0001 0000..., so A15 A14 A13 A12 = 0001. (Key point: Address blocks) 4. Which signals gate the output-port latch and the input-port buffer? A. Both use WR' B. Output select with WR' for the latch, input select with RD' for the 74LS244 buffer C. Output uses RD' and input uses WR' D. Both use IO/M only Answer: B. Writing to the output latch needs WR'; reading through the tri-state buffer needs RD'. (Key point: Control signals) ## Related in Instrumentation II - [Input/output interface unit design factors](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-interface-unit-importance) — Instrumentation II, chapter 7 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1 - [I/O mapped vs memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aiomapped-vs-memmapped) — Instrumentation II, chapter 2 - [8255 at A0A0H: interface and control words](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-a0a0h-control-words) — Instrumentation II, chapter 2 - [Full vs partial address decoding for memory](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Afull-vs-partial-decoding) — Instrumentation II, chapter 2 ## Related in other subjects - [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4 - [Memory-mapped I/O reduces address space](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Ammio-address-space) — Computer Organization and Architecture, chapter 7 - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Space switch design with connection memory](https://www.bctengineer.com/question.md?key=semester_8%2Ftelecommunications%3Aspace-switch-connection-memory) — Telecommunications, chapter 4