--- title: "Parallel transfer schemes and 8255A block diagram" subject: "Instrumentation II" chapter: 2 key: "semester_5/instrumentation_ii:parallel-transfer-8255-block" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/parallel-transfer-8255-block site: BCT Engineering --- # Parallel transfer schemes and 8255A block diagram Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System - Asked in: 2074 Chaitra, 4+4 marks - Video: [8255 Programmable Peripheral Interface: Block Diagram and Working Explained](https://www.youtube.com/watch?v=JCAjbuvvXbA) — Engineering Funda - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/parallel-transfer-8255-block - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2 ## Question Explain the different schemes of parallel data transfer with suitable timing diagram. Explain the functional block diagram of 8255A PPI with neat diagram. ## Short answer Parallel transfer schemes include simple (unconditional) I/O, strobed I/O, and handshake I/O. The 8255 block diagram contains a data bus buffer, read/write control logic, Group A (port A, upper C) and Group B (port B, lower C). It operates in mode 0 (basic I/O), mode 1 (strobed), mode 2 (bidirectional), and bit set/reset mode. ## Answer #### Schemes of parallel data transfer 1. **Simple (unconditional / synchronous) I/O:** device is always ready (switches, LEDs); the CPU reads or writes directly with IN/OUT, no handshake. 2. **Strobed I/O (single handshake / polled):** the device gives a strobe when data is valid; the CPU checks a status flag then reads. 3. **Handshake (double handshake) I/O:** both sides exchange signals (STB' / IBF for input, OBF' / ACK' for output). Used for slow peripherals like printers; supports polled or interrupt (INTR) transfer. 4. **Interrupt driven and DMA** for further efficiency. #### Timing: strobed input (8255 mode 1) ```text Data ----< valid data >------------ STB' ------\______/--------------- IBF ________/-----------\________ (cleared by RD' rising) INTR ____________/--------\_______ RD' -----------------\____/------ ``` STB' low loads the data into the port latch; IBF goes high to tell the device "buffer full"; INTR goes high (if INTE set) to interrupt the CPU; RD' from the CPU resets IBF and INTR. #### Timing: output with handshake (mode 1) ```text WR' ---\__/--------------------- OBF' -----\___________/--------- ACK' ----------------\___/------ INTR ______________________/---- ``` #### Functional block diagram of 8255A ```text D0-D7 <-> [Data bus buffer] +--> [Group A control] -> PA0-PA7 RD',WR' ->[Read/Write control]| [Port A] A0,A1 -> [ logic ] | [Port C upper] PC4-PC7 CS',RESET | +--> [Group B control] -> PB0-PB7 [Port B] [Port C lower] PC0-PC3 ``` - **Data bus buffer:** 8-bit bidirectional buffer to the system bus. - **Read/write control logic:** uses CS', A0, A1, RD', WR', RESET to select ports/control register and direction. - **Group A:** port A and upper port C (PC7-PC4). **Group B:** port B and lower port C (PC3-PC0). - Operating modes: mode 0 (basic I/O), mode 1 (strobed I/O), mode 2 (bidirectional, port A only), and BSR (bit set/reset of port C). | CS' | A1 | A0 | Selected | |---|---|---|---| | 0 | 0 | 0 | Port A | | 0 | 0 | 1 | Port B | | 0 | 1 | 0 | Port C | | 0 | 1 | 1 | Control register | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. In simple (unconditional) parallel I/O, how does the CPU transfer data? A. It waits for a strobe and then checks a status flag B. It exchanges STB' and IBF signals with the device C. Directly with IN/OUT, because the device is always ready and no handshake is used D. It uses DMA to move each byte Answer: C. Simple I/O is for always-ready devices such as switches and LEDs, so no handshake is needed. (Key point: Simple I/O) 2. In 8255 mode 1 strobed input, what does the falling edge of STB' do? A. Clears IBF and INTR B. Loads the data into the port latch and makes IBF go high C. Makes the CPU's RD' go low D. Sends data from the 8255 to the device Answer: B. STB' low latches the data and IBF goes high to tell the device the buffer is full. (Key point: Mode 1 input timing) 3. What clears IBF and INTR in strobed input mode 1? A. The falling edge of STB' B. The rising edge of RD' when the CPU reads the data C. Setting INTE D. Only the RESET signal Answer: B. Reading the port with RD' tells the 8255 the data was taken, so IBF and INTR reset. (Key point: Clearing IBF) 4. Which pins belong to Group B of the 8255A? A. Port B and lower port C (PC3-PC0) B. Port A and upper port C (PC7-PC4) C. Port A and port B D. Port C only Answer: A. Group A is port A plus PC7-PC4; Group B is port B plus PC3-PC0. (Key point: 8255 groups) ## Related in Instrumentation II - [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2 - [Data logger block diagram and operation](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adl-block) — Instrumentation II, chapter 5, asked 6× - [Compact data logger characteristics and block diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acompact-dl-block) — Instrumentation II, chapter 5 - [Centronics printer with 8255A in mode 1](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acentronics-printer-8255-mode1) — Instrumentation II, chapter 2 - [8255 mode 2 operation with timing diagram](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode2) — Instrumentation II, chapter 2 - [Keyboard and printer with 8255A at 4044H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Akbd-printer-ppi-4044h) — Instrumentation II, chapter 2 ## Related in other subjects - [Functional block diagram of excitation control](https://www.bctengineer.com/question.md?key=semester_7%2Fpower_plant_equipment%3Aexcitation-control-block-diagram) — Power Plant Equipment, chapter 3 - [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6× - [Modes of parallel data transfer](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aparallel-data-transfer-modes) — Microprocessor, chapter 4 - [Armature-controlled DC motor transfer function and block diagram](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Atf-armature-dc-motor) — Control Systems, chapter 2