---
title: "PCI bus in brief"
subject: "Instrumentation II"
chapter: 2
key: "semester_5/instrumentation_ii:pci-bus"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/pci-bus
site: BCT Engineering
---

# PCI bus in brief

Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System

- Asked in: 2071 Chaitra, 2 marks; 2073 Chaitra, 2 marks (asked 2 times)
- Video: [io interface with PCI |USB | SCSI | COA | Lec-56 | Bhanu Priya](https://www.youtube.com/watch?v=Ln417iwAGL0) — Education 4u
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/pci-bus
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2

## Question

Write a short note on PCI Bus.

## Short answer

PCI is a 32/64-bit, 33/66 MHz local bus with multiplexed address/data lines, supporting plug-and-play, bus mastering, and burst transfers. Peak bandwidth is 132 MB/s (32-bit, 33 MHz) up to 528 MB/s (64-bit, 66 MHz). It connects to the CPU through a host bridge and replaced ISA.

## Answer

**PCI (Peripheral Component Interconnect)** is a high-speed local bus developed by Intel for connecting peripheral cards to the processor of a PC.

- Data bus 32 bit (extendable to 64 bit); clock 33 MHz (or 66 MHz). Peak bandwidth: 32 bit x 33 MHz = 132 MB/s, and 528 MB/s for 64 bit at 66 MHz.
- **Multiplexed** address/data lines (AD0-AD31) reduce pin count.
- **Plug and play:** configuration space lets the BIOS assign addresses and interrupts automatically.
- **Bus mastering and burst transfers**; connected to the CPU through a host bridge, independent of the processor type.
- Supports 5 V/3.3 V cards; replaced ISA, and later extended by PCI Express.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the peak bandwidth of 32-bit PCI at 33 MHz?
   A. 132 MB/s
   B. 66 MB/s
   C. 264 MB/s
   D. 528 MB/s
   Answer: A. 32 bits = 4 bytes x 33 MHz = 132 MB/s. (Key point: Bandwidth)

2. Why are PCI address/data lines multiplexed?
   A. To increase clock
   B. To reduce pin count
   C. To remove bus master
   D. To lower voltage
   Answer: B. AD0-AD31 carry address and data at different times. (Key point: Multiplexed lines)

3. What does PCI configuration space allow?
   A. Manual jumpers only
   B. Fixed IRQs
   C. BIOS to assign addresses and interrupts automatically
   D. No configuration
   Answer: C. This is the plug and play feature. (Key point: Plug and play)

## Related in Instrumentation II

- [ISA bus signals; replacement by PCI bus](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aisa-pci-bus) — Instrumentation II, chapter 2
- [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2

## Related in other subjects

- [Port-based and bus-based I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aport-based-vs-bus-based-io) — Embedded System, chapter 5, asked 2×
- [Why infinite bus frequency and voltage stay constant](https://www.bctengineer.com/question.md?key=semester_4%2Fpower_system_analysis_i%3Ainfinite-bus-constant-frequency) — Power System Analysis I, chapter 1