---
title: "8255 at A0A0H: interface and control words"
subject: "Instrumentation II"
chapter: 2
key: "semester_5/instrumentation_ii:ppi-a0a0h-control-words"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/ppi-a0a0h-control-words
site: BCT Engineering
---

# 8255 at A0A0H: interface and control words

Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System

- Asked in: 2070 Asar, 4+4 marks
- Video: [8255 Programming Guide: Control Word, Interfacing, and Addressing Details](https://www.youtube.com/watch?v=D9baeIvRXZo) — Engineering Funda
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/ppi-a0a0h-control-words
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2

## Question

The addresses captured by 8255 PPI are A0A0H to A0A3H. Sketch the interfacing circuit with 8085 microprocessor in memory mapped I/O for same. What will be the control words for following configurations of 8255 PPI? (a) Port A: Mode 0 output, Port B: Mode 0 input, Port C: Mode 0 output. (b) Port A: Mode 1 output, Port B: Mode 1 input, PC4,5: output. (c) Port A: Mode 2, Port B: Mode 1 output. (d) Set PC5 in BSR mode.

## Short answer

Addresses: A=A0A0H, B=A0A1H, C=A0A2H, control=A0A3H. Control words: (a) 82H (mode 0: A out, B in, C out); (b) A6H (mode 1: A out, B in, PC4,5 out); (c) C4H (mode 2: A, B mode 1 out); (d) 0BH (BSR set PC5).

## Answer

#### Interfacing circuit (8085, memory mapped)
A0A0H = 1010 0000 1010 0000, so A15-A2 = 1010 0000 1010 00. A1 and A0 go to the 8255 A1 and A0. Lines that must be 1 (A15, A13, A7, A5) are connected directly, and lines that must be 0 (A14, A12, A11, A10, A9, A8, A6, A4, A3, A2) go through inverters.
```text
 A15, A13, A7, A5 -----------------------------+
 A14, A12, A11, A10, A9, A8, A6, A4, A3, A2    |
   (each through a NOT gate) ------------------+--[ 15-input NAND ]--> CS' (low when selected)
 IO/M --[NOT]----------------------------------+   (memory cycle)
 A1 -> A1, A0 -> A0     RD' -> RD'     WR' -> WR'
 AD0-AD7 -> D0-D7       RESET OUT -> RESET
```
In practice two 74LS138 decoders or 74LS30/74LS260 gates are used to build the wide condition. Ports: A = A0A0H, B = A0A1H, C = A0A2H, control = A0A3H.

#### Control words
| Case | Bits (D7..D0) | Control word |
|---|---|---|
| (a) A mode 0 out, B mode 0 in, C mode 0 out | 1 00 0 0 0 1 0 | **82H** |
| (b) A mode 1 out, B mode 1 in, PC4,5 output | 1 01 0 0 1 1 0 | **A6H** |
| (c) A mode 2, B mode 1 output | 1 1x x x 1 0 x | **C4H** (x = 0) |
| (d) Set PC5 (BSR) | 0 xxx 101 1 | **0BH** |

Explanation: D7 = 1 selects mode set; D6 D5 give the group A mode; D4 = port A direction (1 = input); D3 = port C upper direction; D2 = group B mode; D1 = port B direction; D0 = port C lower direction. In (b), PC6 and PC7 (ACK_A', OBF_A') and PC0-PC2 (port B mode 1 signals) are used by the handshake and PC3 is INTR_A; D3 = 0 makes the free pins PC4 and PC5 outputs. In (c), mode 2 ignores D4 and D3. For BSR, D7 = 0, D3-D1 = bit number (101 = 5), and D0 = 1 for set.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For addresses A0A0H-A0A3H, which A15-A2 pattern must be decoded?
   A. 0101 1111 0101 11
   B. 1010 0000 1010 00
   C. 1010 1010 0000 00
   D. 0000 1010 1010 00
   Answer: B. A0A0H = 1010 0000 1010 0000; A1 A0 are free, so A15-A2 = 1010 0000 1010 00. (Key point: Address bits)

2. What is the control word for A mode 0 output, B mode 0 input, C output?
   A. 82H
   B. 92H
   C. 83H
   D. 80H
   Answer: A. D7=1, D4=0, D1=1 gives 1000 0010 = 82H. (Key point: Case (a))

3. What is the control word for A mode 2, B mode 1 output (x = 0)?
   A. C4H
   B. C0H
   C. C6H
   D. A4H
   Answer: A. 1 1x x x 1 0 x gives 1100 0100 = C4H. (Key point: Case (c))

4. What is the BSR word to set PC5?
   A. 0AH
   B. 05H
   C. 0DH
   D. 0BH
   Answer: D. D7=0, bit 5 = 101 in D3-D1, D0 = 1 gives 0000 1011 = 0BH. (Key point: BSR)

## Related in Instrumentation II

- [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4
- [8255A at 80H: addresses, mode 0/1 words, BSR](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-80h-addresses-control) — Instrumentation II, chapter 2
- [8255 mode 1 keyboard and printer with decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-keyboard-printer-mode1-fig) — Instrumentation II, chapter 2
- [Memory-mapped I/O design for 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Amemmapped-io-design-1000h) — Instrumentation II, chapter 2
- [8255 port addresses from decoder figure](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-port-addresses-decoder-fig) — Instrumentation II, chapter 2
- [PC based concrete purifying factory with 8255](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aconcrete-purifying-ppi-4000h) — Instrumentation II, chapter 2

## Related in other subjects

- [Memory capacity from range and interfacing](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amemory-range-capacity-interfacing) — Microprocessor, chapter 4
- [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4
- [Short note: I/O mapped and memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aio-mapped-memory-mapped-io) — Microprocessor, chapter 4
- [Unique/non-unique decoding, memory mapped I/O](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aunique-nonunique-decoding-memory-mapped-io) — Microprocessor, chapter 4