---
title: "8255 port addresses from decoder figure"
subject: "Instrumentation II"
chapter: 2
key: "semester_5/instrumentation_ii:ppi-port-addresses-decoder-fig"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/ppi-port-addresses-decoder-fig
site: BCT Engineering
---

# 8255 port addresses from decoder figure

Instrumentation II · Chapter 2: Parallel Interfacing With Microprocessor Based System

- Asked in: 2072 Chaitra, 3 marks
- Video: [Unit 3 L10.3 | Port Address Calculation in 8255 PPI | Port Address Calculation](https://www.youtube.com/watch?v=_1UboZK6aAw) — Techno Tutorials ( e-Learning)
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/ppi-port-addresses-decoder-fig
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-2

## Question

Specify the addresses for the ports of 8255 PPI shown in figure below. [Figure: Address lines A9 to A6 go to a NAND gate whose output (inverted) drives the active-low enable E2 of a 3x8 decoder. Address lines A15 to A10 go to a second gate whose output drives enable E3. A5 drives the active-low enable E1. A4, A3, A2 are the decoder select inputs. The decoder output O6 (active low) drives CS (active low) of the 8255. Address lines A0 and A1 connect to the 8255 pins A1 and A0 respectively. The 8255 has a data bus connection, ports PA, PB, PC, and RD and WR inputs.]

## Short answer

Decoding: A15-A10=0, A9-A6=1, A5=0, A4A3A2=110 selects O6. Base address 03D8H; ports A, B, C, control at 03D8H, 03D9H, 03DAH, 03DBH.

## Answer

#### Assumptions about the figure
- E2 is active low and is driven through the NAND gate: it is enabled (0) when A9, A8, A7, A6 are all 1.
- E3 is active high and is driven by a gate of A15-A10 that gives 1 only when all of them are 0 (NOR).
- E1 is active low, driven by A5: enabled when A5 = 0.
- The decoder select inputs are C = A4, B = A3, A = A2. Output O6 (active low) means CBA = 110: A4 = 1, A3 = 1, A2 = 0.
- A1 and A0 select the register of the 8255.

#### Address calculation
```text
 Line:  A15 A14 A13 A12 A11 A10 | A9 A8 A7 A6 | A5 | A4 A3 A2 | A1 A0
 Value:  0   0   0   0   0   0  |  1  1  1  1 |  0 |  1  1  0  |  x  x
 Binary: 0000 0011 1101 1000 (A1A0 = 00)
```
Base address = 0000 0011 1101 1000 = **03D8H**.

| A1 A0 | Port | Address |
|---|---|---|
| 0 0 | Port A | 03D8H |
| 0 1 | Port B | 03D9H |
| 1 0 | Port C | 03DAH |
| 1 1 | Control register | 03DBH |

All 16 address lines are decoded, so the address is unique (full decoding): 03D8H-03DBH.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Output O6 of the decoder with C=A4, B=A3, A=A2 corresponds to which A4 A3 A2?
   A. 1 1 0
   B. 0 1 1
   C. 1 0 1
   D. 1 1 1
   Answer: A. O6 means CBA = 110, so A4=1, A3=1, A2=0. (Key point: Decoder output)

2. For E2 (active low, NAND of A9-A6) to be enabled, what must A9-A6 be?
   A. All 0
   B. A9=1 and others 0
   C. Alternating 1010
   D. All 1
   Answer: D. A NAND gives 0 only when all inputs are 1, enabling active-low E2. (Key point: Enables)

3. What is the base address of the 8255?
   A. 03D0H
   B. 3DD8H
   C. 03C8H
   D. 03D8H
   Answer: D. A15-A10=000000, A9-A6=1111, A5=0, A4A3A2=110, A1A0=00 gives 0000 0011 1101 1000 = 03D8H. (Key point: Base address)

## Related in Instrumentation II

- [8255 mode 1 keyboard and printer with decoding](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-keyboard-printer-mode1-fig) — Instrumentation II, chapter 2
- [Double handshake data transfer with 8255-PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adouble-handshake-8255) — Instrumentation II, chapter 2
- [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2
- [Technical benefits of 8255 PPI](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-benefits) — Instrumentation II, chapter 2, asked 2×
- [8255 mode 0 DIP switches and LEDs](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Appi-mode0-dip-leds) — Instrumentation II, chapter 2
- [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4

## Related in other subjects

- [Address decoding for input and output ports](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-input-output-port-block-decoder) — Microprocessor, chapter 4
- [Address decoding for 8 LEDs output port](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-output-port-8-leds) — Microprocessor, chapter 4
- [CMOS NAND gate; totem-pole output](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-nand-totem-pole) — Digital Logic, chapter 10
- [Address decoding with PROM decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aaddress-decoding-prom) — Microprocessor, chapter 4