--- title: "8086 RAM/EPROM interfacing with reset address" subject: "Instrumentation II" chapter: 1 key: "semester_5/instrumentation_ii:rom-ram-8086-fffffh" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/rom-ram-8086-fffffh site: BCT Engineering --- # 8086 RAM/EPROM interfacing with reset address Instrumentation II · Chapter 1: Microprocessor Based Instrumentation System - Asked in: 2068 Baisakh (old course), 10 marks - Video: [SEMICONDUCTOR MEMORY INTERFACING 8086](https://www.youtube.com/watch?v=28GE1jiGzb4) — THE LEARNER - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/rom-ram-8086-fffffh - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-1 ## Question Interface two 8K RAM chips and two 4K EPROM chips with 8086 so as to form a completely working system configuration. We know that, after reset, 8086 starts from address FFFF0H. Select the starting address of EPROM such that this address (FFFF0H) lies in it. The RAM address must start at 00000H. ## Short answer Two 8K RAM chips (16 KB) are placed at 00000H–03FFFH and two 4K EPROM chips (8 KB) at FE000H–FFFFFH to include reset address FFFF0H. Address lines A1–A13 for RAM, A1–A12 for EPROM; A0 and BHE select even/odd banks. A decoder with M/IO high selects EPROM when A19–A13=1111111 and RAM when A19–A14=000000. ## Answer The 8086 has a 16-bit data bus, so memory is built as two banks: an **even bank** (D0-D7, selected by A0 = 0) and an **odd bank** (D8-D15, selected by BHE' = 0). Each bank has one RAM and one EPROM chip. #### Address map - EPROM: two 4K chips = 8 KB. It must contain FFFF0H, so it is placed at the top: **FE000H-FFFFFH**. Each chip needs 12 lines (A1-A12). Select when A19-A13 = 1111111. - RAM: two 8K chips = 16 KB at **00000H-03FFFH**. Each chip needs 13 lines (A1-A13). Select when A19-A14 = 000000. | Memory | A19..A14 | A13 | Range | |---|---|---|---| | RAM 2 x 8K | 000000 | x | 00000H-03FFFH | | EPROM 2 x 4K | 111111 | 1 | FE000H-FFFFFH | (Check: 03FFFH - 00000H + 1 = 16384 bytes; FFFFFH - FE000H + 1 = 8192 bytes.) #### Chip connections | Chip | Address pins | Bank select | |---|---|---| | RAM even | A1-A13 | A0 = 0 | | RAM odd | A1-A13 | BHE' = 0 | | EPROM even | A1-A12 | A0 = 0 | | EPROM odd | A1-A12 | BHE' = 0 | #### Circuit ```text 8086 (min mode) 74LS373 x3 (ALE) AD0-AD15, A16-A19 -> latches -> A0..A19, BHE' ALE -> G of latches DEN'/DT-R' -> 74LS245 (data) RAMSEL' = OR(A19,A18,A17,A16,A15,A14, M/IO'(inverted)) ROMSEL' = NAND(A19..A13) with M/IO = 1 RAMSEL' + A0 -> CS' of RAM even (A0=0) RAMSEL' + BHE' -> CS' of RAM odd ROMSEL' + A0 -> CS' of EPROM even ROMSEL' + BHE' -> CS' of EPROM odd RD' -> OE' of RAM and EPROM WR' -> WE' of RAM D0-D7 -> even chips, D8-D15 -> odd chips ``` After reset the 8086 starts at CS:IP = FFFF:0000 = FFFF0H, which lies inside the EPROM (FE000H-FFFFFH), where a JMP to the main program is placed. A word access at an even address enables both banks; a byte access enables only one bank. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How does the 8086 select the even and odd memory banks? A. Even bank by A0 = 0 and odd bank by BHE' = 0 B. Even by BHE' = 0, odd by A0 = 0 C. Both by A19 D. By IO/M' only Answer: A. Even bank uses D0-D7 with A0 = 0; odd bank uses D8-D15 with BHE' = 0. (Key point: Even/odd banks) 2. Why is the EPROM placed at FE000H-FFFFFH? A. Because RAM must be there B. The reset start address FFFF0H must lie in it, and 8 KB ends at FFFFFH C. Because EPROM needs 16 KB D. Because 8086 starts at 00000H Answer: B. Two 4K chips are 8 KB, placed at the top so FFFF0H is inside. (Key point: EPROM placement) 3. What is the RAM range for two 8K chips starting at 00000H? A. 00000H-01FFFH B. 00000H-07FFFH C. 00000H-03FFFH D. 00000H-0FFFFH Answer: C. Two 8K chips form 16 KB, which is 4000H bytes. (Key point: RAM range) 4. How many address lines connect to each 4K EPROM? A. 13 lines, A1-A13 B. 12 lines, A0-A11 C. 11 lines, A1-A11 D. 12 lines, A1-A12 Answer: D. 4K = 2^12 and A0 is used for bank selection, so A1-A12. (Key point: Chip address lines) 5. What happens in a word access at an even address? A. Both banks are enabled B. Only the even bank is enabled C. Only the odd bank is enabled D. Neither bank is enabled Answer: A. A0 = 0 and BHE' = 0 together select both bytes. (Key point: Word access) ## Related in Instrumentation II - [Interfacing: 512-byte RAM with 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arag-ram-512-interface) — Instrumentation II, chapter 2 - [DMA concept; ROM/RAM interface at 4000H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Adma-memory-interface-4000h) — Instrumentation II, chapter 1 - [USB interface chips: device vs host](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-interface-chips) — Instrumentation II, chapter 3 - [USB enumeration; device vs host interface chips](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-enumeration) — Instrumentation II, chapter 3 - [8-channel ADC interface with 8255 and 8085](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aadc8-8255-problem) — Instrumentation II, chapter 4 - [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2 ## Related in other subjects - [74LS138 interfacing of ROM, RAM, EPROM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-rom-ram-eprom) — Microprocessor, chapter 4 - [Interface 4 KB EPROM and two 2 KB RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ainterface-4kb-eprom-two-2kb-ram) — Microprocessor, chapter 4 - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4 - [Interfacing 2732 EPROM and 6116 RAM](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-74ls138-2732-6116) — Microprocessor, chapter 4