--- title: "Factors while routing signal traces on PCB" subject: "Instrumentation II" chapter: 8 key: "semester_5/instrumentation_ii:route-factors" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/route-factors site: BCT Engineering --- # Factors while routing signal traces on PCB Instrumentation II · Chapter 8: Circuit Layout - Asked in: 2074 Chaitra, 6 marks; 2072 Kartik, 6 marks; 2072 Chaitra, 6 marks; 2079 Baisakh, 1+2 marks (asked 4 times) - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/route-factors - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-8 ## Question Poor circuit layout and signal propagating principle may cause many problems in the circuit operation, manufacturing ease and probability of design errors. What factors will you consider while routing the signal traces on PCB. ## Short answer Consider trace length and impedance control to avoid reflections, maintain spacing (3W rule) and orthogonal routing to reduce crosstalk, ensure continuous return paths under signals. Also follow manufacturing design rules like minimum trace width/clearance, avoid stubs, and use 45° bends. ## Answer Poor routing causes crosstalk, reflections, EMI, long delays, difficult manufacture and design-rule errors. The main factors are: #### Signal-propagation and electrical factors 1. **Trace length:** keep traces as short and direct as possible, particularly clocks and high-speed lines; match lengths of buses and differential pairs to avoid skew. 2. **Characteristic impedance:** keep trace width and distance from the reference plane constant (e.g. 50 ohm) and terminate lines to prevent reflections. 3. **Crosstalk:** use adequate spacing (3W rule), avoid long parallel runs, route adjacent layers orthogonally, and use guard traces. 4. **Return path:** keep a continuous ground plane under the signal; do not cross plane splits; use stitching vias when the layer changes. 5. **Bends and branches:** use 45-degree bends or arcs, not 90-degree corners (which change the impedance); avoid acute angles (they form acid traps) and avoid stubs and T-branches (use a daisy chain instead). 6. **Vias:** minimise their number, as they add inductance, capacitance and discontinuity. 7. **Current capacity and voltage:** choose a width suited to the current and temperature rise (power traces wider), and keep clearance and creepage for high voltage. 8. **Separate signals:** keep analog, digital and power separate, and keep sensitive signals away from noisy ones. #### Manufacturing factors - Follow the fabricator's design rules: minimum trace width/spacing, hole size, annular ring, and clearance from the board edge. - Use teardrops at pads, avoid thin necks, and avoid acid traps (acute angles). - Use uniform copper distribution to prevent warping; consider solder-mask and silkscreen aspects. #### Design-error and testing factors - Run design-rule check (DRC) and electrical-rule check (ERC); place test points, and label components; consider thermal relief for pads connected to planes. - Leave room for rework and component accessibility. Following these controls keeps the design reliable, manufacturable and low-noise. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What should be done with traces of buses and differential pairs? A. Match lengths to avoid skew B. Make them as different as possible C. Add stubs D. Route over plane splits Answer: A. Length matching avoids timing skew. (Key point: Trace length and skew) 2. Why use 45-degree bends instead of 90-degree corners? A. 90-degree corners are cheaper B. To avoid impedance change and acute-angle acid traps C. To lengthen the trace D. To increase vias Answer: B. Sharp corners change impedance, and acute angles trap etchant. (Key point: Bends) 3. What is needed for a good return path? A. Slots in the plane under the trace B. Crossing plane splits C. A continuous ground plane under the signal, with stitching vias at layer changes D. A separate long return wire Answer: C. Continuous return avoids detours that raise noise and EMI. (Key point: Return path) 4. Why minimise the number of vias? A. They add inductance, capacitance and discontinuity B. They are not allowed by fabricators C. They reduce current capacity only D. They remove the ground plane Answer: A. Each via is an impedance discontinuity. (Key point: Vias) ## Related in Instrumentation II - [Terminologies in routing signal traces](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arouting-terminologies) — Instrumentation II, chapter 8 - [Routing factors and avoiding crosstalk](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aroute-factors-crosstalk) — Instrumentation II, chapter 8 - [Reducing crosstalk in PCB routing](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Acrosstalk-routing) — Instrumentation II, chapter 8, asked 5× - [High speed circuit design guidelines](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ahigh-speed-guidelines) — Instrumentation II, chapter 7, asked 3× - [Ground, returns and shields in circuit layout](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aground-returns-shields) — Instrumentation II, chapter 8 - [Routing rules for crosstalk and impedance matching](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Arules-mismatch-crosstalk) — Instrumentation II, chapter 8, asked 3× ## Related in other subjects - [Permeability as root cause of poor durability](https://www.bctengineer.com/question.md?key=semester_5%2Fconcrete_technology_and_masonry_structure%3Apermeability-root-cause-durability) — Concrete Technology and Masonry Structure, chapter 6, asked 3× - [Material handling and factors to consider](https://www.bctengineer.com/question.md?key=semester_8%2Fconstruction_management%3Amaterial-handling-factors) — Construction Management, chapter 6 - [EDM operation principles and errors](https://www.bctengineer.com/question.md?key=semester_3%2Fsurveying_i%3Aedm-operation-and-errors) — Surveying I, chapter 2, asked 2× - [Errors encountered during file operation](https://www.bctengineer.com/question.md?key=semester_3%2Fobject_oriented_programming%3Afile-errors) — Object Oriented Programming, chapter 8