--- title: "Error detection in serial data transmission" subject: "Instrumentation II" chapter: 3 key: "semester_5/instrumentation_ii:serial-error-detection" source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/serial-error-detection site: BCT Engineering --- # Error detection in serial data transmission Instrumentation II · Chapter 3: Serial Interfacing With Microprocessor Based System - Asked in: 2074 Chaitra, 3 marks; 2072 Chaitra, 4 marks (asked 2 times) - Video: [Error Detection](https://www.youtube.com/watch?v=EMrY-8m8D1E) — Neso Academy - Answer checked by Claude Sonnet 5.5 on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/serial-error-detection - Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-3 ## Question Describe the various error detection techniques used in serial data transmission. ## Short answer Error detection in serial transmission uses parity (odd/even bit count), checksum (two's complement sum), CRC (polynomial division for burst errors), and UART-detected errors like parity, framing, and overrun. ## Answer Errors in serial transmission are caused by noise, timing differences and interference. Common detection techniques are: #### 1. Parity check (VRC, Vertical Redundancy Check) An extra bit is added to each character so that the total number of 1s is even (even parity) or odd (odd parity). The receiver recomputes it. Detects all single-bit errors (and any odd number of bit errors), but not an even number of errors. Example: data 1011001 (four 1s) -> even parity bit = 0; odd parity bit = 1. #### 2. Longitudinal redundancy check (LRC) A parity bit is calculated for each bit column over a block of characters, and the resulting block check character is sent at the end. With VRC it detects most burst errors. #### 3. Checksum Bytes of the block are added (modulo 256) and the two's complement of the sum is sent. The receiver adds all bytes plus the checksum; the result must be zero. #### 4. Cyclic redundancy check (CRC) The data block is treated as a polynomial and divided (modulo 2) by a generator polynomial (e.g. CRC-16: x^16 + x^15 + x^2 + 1; CRC-CCITT: x^16 + x^12 + x^5 + 1). The remainder (CRC bits) is appended; the receiver divides again and a non-zero remainder means error. It detects all burst errors up to the CRC length and most others. Used in USB, Ethernet, disk. #### 5. UART-detected errors - **Parity error:** parity does not match. - **Framing error:** stop bit not found where expected (wrong baud rate or noise). - **Overrun error:** a new character arrives before the previous one was read. - **Break detection:** line low for more than one frame. #### 6. Others Echo (loopback) checking, handshaking with ACK/NAK and retransmission (ARQ), and forward error correction (Hamming code) that can also correct errors. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What errors can a single parity bit not detect? A. Single-bit errors B. Odd number of bit errors C. An even number of bit errors D. All errors Answer: C. Parity detects odd numbers of bit errors but misses an even number. (Key point: Parity limits) 2. For data 1011001 (four 1s), what is the even parity bit? A. 1 B. 0 C. Either D. None needed Answer: B. Four 1s is already even, so the even parity bit is 0 (odd parity bit is 1). (Key point: Even parity example) 3. How does CRC detect errors? A. Add bytes and send the sum B. Divide data polynomial by generator, send remainder; non-zero remainder at receiver means error C. Count the ones D. Echo the data back Answer: B. CRC uses modulo-2 polynomial division and appends the remainder. (Key point: CRC) 4. What is a framing error in a UART? A. Parity mismatch B. Stop bit not found where expected C. New character before the old was read D. Line low longer than a frame Answer: B. Framing error: no stop bit at the expected place (wrong baud rate or noise). Overrun is the unread-character case. (Key point: Framing error) ## Related in Instrumentation II - [Data transfer techniques for slow I/O](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aio-speed-mismatch) — Instrumentation II, chapter 1, asked 3× - [Why serial transfer is preferred over parallel](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aserial-vs-parallel-preferred) — Instrumentation II, chapter 3 - [Asynchronous serial transfer of a character](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aasync-7bit-ascii-2stop) — Instrumentation II, chapter 3 - [Digital transmission system; analog vs digital](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aanalog-digital-transmission-compare) — Instrumentation II, chapter 5 - [Character transmission time at 1200 baud](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Abaud-time-1200) — Instrumentation II, chapter 3, asked 2× - [Synchronous vs asynchronous transmission](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Async-vs-async) — Instrumentation II, chapter 3 ## Related in other subjects - [Synchronous vs asynchronous serial transmission](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Async-async-serial) — Microprocessor, chapter 4, asked 3× - [Dataword vs codeword; error coding techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Adataword-codeword-error-coding) — Data Communication, chapter 8 - [CRC error detection with example](https://www.bctengineer.com/question.md?key=semester_5%2Fdata_communication%3Acrc-explain) — Data Communication, chapter 8, asked 5× - [Error correction vs detection, bit stuffing](https://www.bctengineer.com/question.md?key=semester_7%2Fcomputer_networks_and_security%3Aerror-correct-detect-bitstuff) — Computer Networks and Security, chapter 3