---
title: "USB signals and bus states"
subject: "Instrumentation II"
chapter: 3
key: "semester_5/instrumentation_ii:usb-signals-bus-states"
source: https://www.bctengineer.com/q/semester_5/instrumentation_ii/usb-signals-bus-states
site: BCT Engineering
---

# USB signals and bus states

Instrumentation II · Chapter 3: Serial Interfacing With Microprocessor Based System

- Asked in: 2072 Kartik, 4 marks
- Video: [USB Protocol Explained: Basics, Versions, Connectors, Working, Signals, and Objectives](https://www.youtube.com/watch?v=6knlPjpa_DE) — Engineering Funda
- Answer checked by Claude Sonnet 5.5 on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_5/instrumentation_ii/usb-signals-bus-states
- Whole chapter: https://www.bctengineer.com/md/semester_5/instrumentation_ii/chapter-3

## Question

Explain the USB signals and associated bus states. Also mention the signal levels to achieve these bus states.

## Short answer

USB uses differential D+ and D- with NRZI coding. Bus states: J (D+ high, D- low) idle, K (D+ low, D- high) data, SE0 (both low) for EOP and reset. Full-speed devices pull D+ up with 1.5 kΩ; low-speed pull D- up. Hosts have 15 kΩ pull-downs.

## Answer

USB uses a four-wire cable: VBUS (+5 V), D-, D+ and GND. Data is sent on the twisted pair D+ and D- by **differential signalling** (NRZI coding with bit stuffing). The voltage combination on D+ and D- defines the **bus state**.

#### Bus states and signal levels (full speed, 3.3 V logic)
| State | D+ | D- | Meaning |
|---|---|---|---|
| Differential 1 (J state) | High (> 2.8 V) | Low (< 0.3 V) | Idle, and data bit "J" |
| Differential 0 (K state) | Low (< 0.3 V) | High (> 2.8 V) | Data bit "K", resume signalling |
| Single-ended zero (SE0) | Low (< 0.8 V) | Low (< 0.8 V) | End of packet (2 bit times), reset (> 10 ms), disconnect |
| Single-ended one (SE1) | High | High | Illegal state |
| Idle | J state | | Bus idle between packets |
| Resume | K state for at least 20 ms | | Wake-up from suspend |
| Reset | SE0 for at least 10 ms | | Device returns to default state |

For low-speed devices the polarity is reversed: J has D- high and D+ low, K is the opposite.

#### Speed detection
A full-speed device has a 1.5 kohm pull-up on D+ to 3.3 V, and a low-speed device on D-. The host has 15 kohm pull-down resistors on both lines. When a device is attached, the line with the pull-up goes high, giving the J state, and the host detects connect and the speed. Disconnect is recognised as SE0 (both pull-downs) for more than 2.5 us.

#### Packet signalling
Idle (J) -> SYNC (KJKJKJKK) -> packet -> EOP (SE0, SE0, J) -> Idle.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. In full-speed USB, which D+/D- levels give the J state?
   A. Both low
   B. D+ low, D- high
   C. Both high
   D. D+ high, D- low
   Answer: D. J state (differential 1) has D+ above 2.8 V and D- below 0.3 V; it is also the idle state. (Key point: J and K states)

2. What does the single-ended zero (SE0) state signify?
   A. Start of SYNC
   B. Resume signalling
   C. Idle between packets
   D. End of packet, reset (>10 ms) or disconnect
   Answer: D. Both lines low is SE0: two bit times mark EOP, over 10 ms means reset, and it also shows disconnect. (Key point: SE0 uses)

3. Which bus state is illegal in USB?
   A. SE0
   B. K state
   C. SE1 (both D+ and D- high)
   D. J state
   Answer: C. SE1 has both lines high and must never occur. (Key point: Illegal state)

4. How do J and K differ for a low-speed device compared with full speed?
   A. Only voltage is lower
   B. J becomes SE0
   C. Polarity is reversed
   D. They are identical
   Answer: C. For low-speed, J has D- high and D+ low, the opposite of full speed. (Key point: Low-speed polarity)

## Related in Instrumentation II

- [ISA bus signals; replacement by PCI bus](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aisa-pci-bus) — Instrumentation II, chapter 2
- [Types of USB packets](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-packet-types) — Instrumentation II, chapter 3, asked 3×
- [USB to RS-232 adapter design](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ausb-rs232-adapter) — Instrumentation II, chapter 3
- [PCI bus; 8255 printer interface at 5500H](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Apci-printer-5500h) — Instrumentation II, chapter 2

## Related in other subjects

- [Digital IC signal levels and Gray code](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Aic-signal-levels-gray-code) — Digital Logic, chapter 1, asked 2×
- [TTL input and output signal levels](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Attl-signal-levels) — Digital Logic, chapter 10, asked 2×
- [PCM bit rate for 4.5 MHz TV signal with 1024 levels](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Apcm-tv-4-5mhz-1024) — Communication Systems, chapter 4
- [PAM, PWM, PPM; PCM of 4.8 MHz TV signal with 512 levels](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Apam-pwm-ppm-tv-4-8mhz) — Communication Systems, chapter 4