---
title: "Short note: Phase locked loop"
subject: "Communication Systems"
chapter: 2
key: "semester_6/communication_systems:short-note-pll"
source: https://www.bctengineer.com/q/semester_6/communication_systems/short-note-pll
site: BCT Engineering
---

# Short note: Phase locked loop

Communication Systems · Chapter 2: Amplitude Modulation

- Asked in: 2079 Chaitra (CS I), 5 marks; 2067 Shrawan (CS I), 5 marks (asked 2 times)
- Video: [What is Phase Lock Loop (PLL)? How Phase Lock Loop Works ? PLL Explained](https://www.youtube.com/watch?v=Q5dC9TbzR9k) — ALL ABOUT ELECTRONICS
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/communication_systems/short-note-pll
- Whole chapter: https://www.bctengineer.com/md/semester_6/communication_systems/chapter-2

## Question

Write a short note on phase locked loop.

## Short answer

A phase-locked loop (PLL) is a feedback circuit that locks a VCO's frequency and phase to an input signal using a phase detector and loop filter. Key parameters are free-running frequency, capture range, and lock range. It is used for FM demodulation, carrier recovery, and frequency synthesis.

## Answer

A **phase-locked loop (PLL)** is a closed-loop feedback circuit that locks the frequency and phase of a voltage-controlled oscillator to those of an input signal.

```text
 vin ->[Phase det]->[Loop filter]->[Amp]--+--> vc (FM out)
           ^                              |
           +------------[ VCO ]<----------+
                       vo (locked output)
```

**Components and working:**
1. **Phase detector** compares the input with the VCO output and gives an error voltage proportional to their phase difference.
2. **Loop filter** (LPF) removes the high-frequency terms and sets the loop response.
3. **VCO** changes its frequency according to the control voltage, $f_o=f_{free}+K_vv_c$, and is pulled toward the input frequency.

When the loop is **locked**, the VCO frequency equals the input frequency, with a small constant phase difference. If the input frequency changes, the error voltage changes and the VCO follows it.

**Key terms:**
- **Free-running frequency:** the VCO frequency with no input.
- **Capture range:** the range of input frequencies over which the loop can acquire lock.
- **Lock (tracking) range:** the range over which the loop stays locked once it has locked; it is wider than the capture range.

**Applications:** FM demodulation (the control voltage is the message), carrier recovery for coherent detection (locking to the carrier or pilot in AM/SSB, or a Costas loop for DSB-SC), frequency synthesizers, frequency multiplication/division, clock recovery in digital receivers, and FSK demodulation. IC example: NE565.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. When a PLL is locked, the VCO frequency is:
   A. Equal to its free-running frequency
   B. Equal to the input frequency with a small constant phase difference
   C. Twice the input frequency
   D. Zero
   Answer: B. Locking means the VCO follows the input frequency, leaving a fixed small phase offset. (Key point: Locked state)

2. How do capture range and lock range compare?
   A. Capture range is wider than lock range
   B. Lock (tracking) range is wider than capture range
   C. They are always equal
   D. Lock range applies only before lock
   Answer: B. A loop can stay locked over a wider range than the range over which it can first acquire lock. (Key point: Capture vs lock range)

3. How does a PLL demodulate FM?
   A. The VCO output is the message
   B. The control voltage vc follows the input frequency variation and is the message
   C. The phase detector output is amplified into the message
   D. The loop filter is removed
   Answer: B. To track a varying frequency the VCO control voltage must vary in proportion, so vc is the demodulated message. (Key point: PLL as FM demodulator)

## Related in Communication Systems

- [Costas loop detector and phase error correction](https://www.bctengineer.com/question.md?key=semester_6%2Fcommunication_systems%3Acostas-loop-phase-error) — Communication Systems, chapter 2

## Related in other subjects

- [Nyquist stability of 50/[(s+1)(s+2)] and phase margin](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Anyquist-50-s1-s2-pm) — Control Systems, chapter 6, asked 3×