--- title: "Importance and operation of sample and hold" subject: "Digital Control System" chapter: 1 key: "semester_6/digital_control_system:importance-of-sample-hold" source: https://www.bctengineer.com/q/semester_6/digital_control_system/importance-of-sample-hold site: BCT Engineering --- # Importance and operation of sample and hold Digital Control System · Chapter 1: Introduction to Discrete Time Control System - Asked in: 2072 Magh, 8 marks - Video: [Sample and Hold Circuit](https://www.youtube.com/watch?v=bwPh7oDjHUo) — AK ECE - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/digital_control_system/importance-of-sample-hold - Whole chapter: https://www.bctengineer.com/md/semester_6/digital_control_system/chapter-1 ## Question Why sample and hold circuits are important in discrete time control system? Explain operation of sample and hold circuit in detail. ## Short answer Sample-and-hold circuits provide steady input for ADC conversion, enable fast signal conversion, allow multiplexing and simultaneous sampling, and reconstruct continuous actuator signals. The circuit uses an input buffer, FET switch, hold capacitor, and output buffer. In sample mode the capacitor charges; in hold mode the switch opens trapping the charge. Key specifications include acquisition time, aperture time, droop, feedthrough, and hold step. ## Answer A **sample-and-hold (S/H) circuit** samples an analog signal at an instant and holds that value constant for a given time. #### Why S/H is important 1. **Steady input for the A/D converter:** an ADC (e.g. successive approximation) needs several microseconds to convert. If the input changes during this time by more than half an LSB, the output code is wrong. The S/H freezes the input during conversion. 2. **Allows fast signals to be converted:** without S/H, a 12-bit ADC with 10 µs conversion time can only handle signals of a few hertz; with S/H, much higher frequencies. 3. **Multiplexing:** in a multichannel system one S/H and ADC serve many channels; the S/H keeps each sample while the multiplexer moves on. 4. **Simultaneous sampling:** several S/H circuits can capture many signals at the same instant. 5. **Output hold:** at the D/A side a hold keeps the actuator signal constant between updates (zero order hold), reconstructing a continuous signal. #### Circuit ```text Switch S (FET) Vin --[A1]--o/ o--+--[A2]--> Vout | === C (hold capacitor) | GND Control (sample/hold) --> gate of S ``` - **A1:** input buffer with low output impedance for fast charging of C. - **S:** MOSFET/JFET switch driven by the logic control signal. - **C:** low-leakage hold capacitor. - **A2:** output buffer with very high input impedance so C does not discharge. #### Operation **Sample (tracking) mode:** control signal closes S. C charges through A1 and $V_{out}$ follows $V_{in}$. The time to reach the input value within the required accuracy is the **acquisition time**. **Hold mode:** at the sampling instant the control signal opens S. The charge on C is trapped because neither the open switch nor A2 draws current, so $V_{out}$ remains at $V_{in}(kT)$. The ADC converts this value. ```text Vin /‾‾\ / / \____/ Vout /‾‾‾‾|____|‾‾|___ Mode track hold track hold ``` #### Performance terms - **Acquisition time:** time to charge C to the input value in sample mode. - **Aperture time:** delay between hold command and actual opening of S. - **Droop:** slow decay during hold, $dV/dt = I_{leak}/C$. - **Feedthrough:** input leaking to output during hold. - **Hold step (pedestal):** small jump from charge injected by the switch. Mathematically, the S/H is modelled as an ideal sampler followed by a zero order hold, $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Why is an S/H needed before an ADC? A. To keep the input steady during conversion (within half an LSB) B. To amplify the signal C. To raise the quantization step D. To remove the need for a clock Answer: A. If the input changes during conversion the output code is wrong. (Key point: Need for S/H) 2. In hold mode the output stays constant because: A. C is discharged through A1 B. The switch is open and the buffer A2 draws no current from C C. The switch is closed D. The control signal is zero volts at C Answer: B. Charge is trapped on the capacitor. (Key point: Hold mode) 3. Acquisition time is: A. The delay between hold command and switch opening B. The decay rate in hold C. The time for C to charge to the input value in sample mode D. The input leakage in hold Answer: C. The delay in switch opening is aperture time. (Key point: Acquisition time) 4. Droop rate during hold is: A. C/I_leak B. I_leak x C C. V/RC at zero D. I_leak/C Answer: D. Leakage current discharges the hold capacitor. (Key point: Droop) 5. One S/H and ADC can serve many channels because: A. The S/H holds each sample while the multiplexer moves on B. Each channel has its own ADC C. The ADC stores all channels at once D. The S/H converts to digital Answer: A. It keeps the sample constant for the ADC. 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