---
title: "Quantization problems and improvement"
subject: "Digital Control System"
chapter: 1
key: "semester_6/digital_control_system:quantization-problems-improvement"
source: https://www.bctengineer.com/q/semester_6/digital_control_system/quantization-problems-improvement
site: BCT Engineering
---

# Quantization problems and improvement

Digital Control System · Chapter 1: Introduction to Discrete Time Control System

- Asked in: 2072 Magh, 4 marks
- Video: [Quantization in digital communication - Hindi - Quantization Error, Step Size](https://www.youtube.com/watch?v=Uzwp2n4BZsg) — Electronics Subjectified
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/digital_control_system/quantization-problems-improvement
- Whole chapter: https://www.bctengineer.com/md/semester_6/digital_control_system/chapter-1

## Question

Define problems associated with quantization. How can it be improved?

## Short answer

Quantization introduces error up to ±Q/2, noise variance Q²/12, dead zone, limit cycles, and steady-state error. Improvement: increase ADC bit count, match signal range, use rounding, oversample and average, add dither, and use longer word length in controller.

## Answer

**Quantization** is the rounding of a sampled amplitude to one of a finite number of levels in an A/D converter. For an n-bit ADC with full-scale range $FSR$, the step (quantum) is $Q = FSR/2^n$.

#### Problems caused by quantization

1. **Quantization error:** the difference between true and quantized value; with rounding it lies between $-Q/2$ and $+Q/2$.
2. **Quantization noise:** the error behaves like random noise of variance $Q^2/12$, which reduces signal-to-noise ratio.
3. **Loss of small signals:** changes smaller than $Q$ are not detected (dead zone).
4. **Limit cycles:** in a feedback loop the nonlinearity can cause small sustained oscillations of the output.
5. **Steady-state error:** the output can settle anywhere within one step of the set point.
6. **Coefficient and arithmetic round-off** in the controller with short word length.

#### Ways to improve

- **Increase the number of bits** (e.g. 8 to 12 bits): $Q$ falls by 16 times; SNR rises about 6 dB per bit.
- **Match signal range to ADC range** by proper amplification so all levels are used.
- **Use rounding instead of truncation** to make the error zero-mean.
- **Oversampling and averaging/filtering** to reduce noise.
- **Dithering:** add small noise before quantizing to break limit cycles.
- **Longer word length and careful scaling** in the controller software.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For an n-bit ADC with full-scale range FSR, the quantum is:
   A. Q = FSR/2^n
   B. Q = FSR/n
   C. Q = FSR x 2^n
   D. Q = FSR/(2n)
   Answer: A. There are 2^n levels spanning FSR. (Key point: Quantum size)

2. The quantization error is treated as noise with variance:
   A. Q^2/2
   B. Q^2/12
   C. Q/12
   D. Q^2/4
   Answer: B. Uniform error over +-Q/2 gives variance Q^2/12, which lowers SNR. (Key point: Quantization noise)

3. How can limit cycles caused by quantization be broken?
   A. By using truncation instead of rounding
   B. By lowering the number of bits
   C. By adding dither (small noise) before quantizing
   D. By removing the S/H
   Answer: C. Dither breaks the nonlinearity's sustained oscillation. (Key point: Limit cycles)

4. Increasing the ADC from 8 to 12 bits changes Q by a factor of:
   A. Q falls by 4 times
   B. Q rises by 16 times
   C. Q is unchanged
   D. Q falls by 16 times
   Answer: D. Four extra bits give 2^4 = 16 times more levels; SNR rises about 6 dB per bit. (Key point: Improving resolution)

## Related in Digital Control System

- [Quantization problems and DCS advantages](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Aquantization-problems-advantages) — Digital Control System, chapter 1

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