---
title: "Short note: Sample and hold circuit"
subject: "Digital Control System"
chapter: 1
key: "semester_6/digital_control_system:short-note-sample-hold"
source: https://www.bctengineer.com/q/semester_6/digital_control_system/short-note-sample-hold
site: BCT Engineering
---

# Short note: Sample and hold circuit

Digital Control System · Chapter 1: Introduction to Discrete Time Control System

- Asked in: 2067 Mangsir, 6 marks
- Video: [Sample & Hold Circuit using OpAmp (Basics, Circuit, Working & Waveforms) Explained](https://www.youtube.com/watch?v=JJBQcnxM7lI) — Engineering Funda
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/digital_control_system/short-note-sample-hold
- Whole chapter: https://www.bctengineer.com/md/semester_6/digital_control_system/chapter-1

## Question

Write a short note on sample and hold circuit.

## Short answer

A sample-and-hold circuit captures an analog signal value at the sampling instant and holds it constant during ADC conversion. It consists of an input buffer, FET switch, hold capacitor, and output buffer. In sample mode the output tracks the input; in hold mode the switch opens and the capacitor maintains the voltage. It prevents ADC errors, enables multiplexing, and allows simultaneous sampling. Key specifications are acquisition time, aperture time, droop, and feedthrough.

## Answer

A **sample-and-hold (S/H) circuit** takes the value of an analog signal at a sampling instant and holds it constant for the time the A/D converter needs to convert it. It is placed between the multiplexer and the ADC in a data acquisition system.

```text
           Switch S (FET)
 Vin --[A1]--o/ o--+--[A2]--> Vout
                   |
                  === C (hold capacitor)
                   |
                  GND
     Control (sample/hold) --> gate of S
```

**Components:** input buffer A1 (low output impedance), electronic switch S (FET) driven by a logic control signal, hold capacitor C, and output buffer A2 (high input impedance).

#### Modes

- **Sample/tracking mode:** S closed; C charges and the output follows the input.
- **Hold mode:** S opened at the sampling instant; C keeps its charge and the output stays constant at $V_{in}(kT)$ while the ADC converts.

#### Why it is needed

- The ADC input must not change by more than half an LSB during conversion.
- One S/H and ADC can serve many multiplexed channels.
- Several S/H units allow simultaneous sampling of many signals.

#### Specifications

| Term | Meaning |
|---|---|
| Acquisition time | Time for output to settle to input in sample mode |
| Aperture time | Delay between hold command and switch opening |
| Droop rate | $I_{leak}/C$, fall of voltage during hold |
| Feedthrough | Input appearing at output during hold |

A large C reduces droop but increases acquisition time, so C is chosen as a compromise. In analysis, the S/H is modelled as an ideal sampler followed by a zero order hold with $G_{h0}(s) = \frac{1-e^{-Ts}}{s}$.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. The role of A2 in the S/H circuit is:
   A. Input buffer to charge C quickly
   B. Output buffer with high input impedance so C does not discharge
   C. The switch
   D. The hold capacitor
   Answer: B. A1 is the low-impedance input buffer; A2 is the high-impedance output buffer. (Key point: Components)

2. Choosing a larger hold capacitor C:
   A. Increases droop and shortens acquisition
   B. Has no effect on droop
   C. Reduces droop but increases acquisition time
   D. Removes feedthrough
   Answer: C. Hence C is chosen as a compromise. (Key point: Capacitor choice)

3. The S/H is placed:
   A. After the actuator
   B. Between ADC and CPU
   C. After the DAC only
   D. Between the multiplexer and the ADC
   Answer: D. It freezes the signal for conversion. (Key point: Position)

4. Feedthrough means:
   A. Input appearing at output while in hold mode
   B. Slow decay in hold
   C. Delay of switch opening
   D. Time to settle in sample mode
   Answer: A. It is unwanted leakage of the input signal. (Key point: Feedthrough)

## Related in Digital Control System

- [Sample and hold: tracking and hold modes](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Asample-hold-tracking-hold) — Digital Control System, chapter 1, asked 3×
- [Sample-and-hold capacitor voltage and advantages](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Asample-hold-capacitor-voltage) — Digital Control System, chapter 1
- [Importance and operation of sample and hold](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Aimportance-of-sample-hold) — Digital Control System, chapter 1
- [Short note: Data hold circuit](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Ashort-note-data-hold) — Digital Control System, chapter 1
- [Data hold circuit and ZOH derivation](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Adata-hold-zoh-derivation) — Digital Control System, chapter 1
- [Define tracking and hold mode](https://www.bctengineer.com/question.md?key=semester_6%2Fdigital_control_system%3Adefine-tracking-hold-mode) — Digital Control System, chapter 1, asked 2×

## Related in other subjects

- [Sample and hold circuit](https://www.bctengineer.com/question.md?key=semester_4%2Finstrumentation_i%3Asample-and-hold-circuit) — Instrumentation I, chapter 6