--- title: "8051 data memory organization" subject: "Embedded System" chapter: 9 key: "semester_6/embedded_system:8051-data-memory-organization" source: https://www.bctengineer.com/q/semester_6/embedded_system/8051-data-memory-organization site: BCT Engineering --- # 8051 data memory organization Embedded System · Chapter 9: Microcontrollers in Embedded Systems - Asked in: 2078 Poush, 4 marks - Video: [memory organization in micro control 8051](https://www.youtube.com/watch?v=dwQuyZE8NDs) — a learning room - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/8051-data-memory-organization - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9 ## Question Explain the data memory organization in 8051 microcontroller. ## Short answer Internal data RAM (00H–7FH) contains four register banks (00H–1FH), a bit-addressable area (20H–2FH) of 16 bytes, and 80 bytes general-purpose RAM (30H–7FH). SFRS occupy 80H–FFH; bit-addressable SFRS include ports, PSW, ACC, B. Exteranal data memory up to 64 KB is accessed via MOVX. ## Answer The 8051 has 128 bytes of internal data RAM (addresses 00H-7FH) and a separate SFR area (80H-FFH). More data memory can be added externally (up to 64 KB, accessed by MOVX). ```text FFH +-------------------------+ | SFRs: P0,P1,P2,P3,TCON, | direct addressing only 80H | TMOD,IE,IP,PSW,ACC,B... | 7FH +-------------------------+ | General-purpose RAM | 80 bytes 30H | | 2FH +-------------------------+ | Bit-addressable RAM | 16 bytes = 128 bits 20H | | bit addresses 00H-7FH 1FH +-------------------------+ | Register bank 3 | 18H | Register bank 2 | 10H | Register bank 1 | 08H | Register bank 0 (R0-R7) | 00H +-------------------------+ ``` 1. **Register banks (00H-1FH):** four banks of R0-R7. The active bank is selected by the RS1 and RS0 bits of PSW; bank 0 is the default after reset. 2. **Bit-addressable area (20H-2FH):** 16 bytes giving 128 individually addressable bits, used with SETB, CLR, CPL, JB, JNB. 3. **General-purpose RAM (30H-7FH):** 80 bytes for variables and the stack. The stack pointer is 07H after reset, so the stack starts at 08H (overlapping banks 1-3 unless SP is changed). 4. **SFRs (80H-FFH):** ports, timers, serial buffer, PSW, ACC, B, SP, DPTR. Those with addresses divisible by 8 (P0, TCON, P1, SCON, P2, IE, P3, IP, PSW, ACC, B) are bit-addressable. The 8052 has another 128 bytes at 80H-FFH reachable only by indirect addressing. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How is the 128-byte internal data RAM of the 8051 divided starting from 00H? A. Bit-addressable area, register banks, then general RAM B. Register banks (00H-1FH), bit-addressable area (20H-2FH), general-purpose RAM (30H-7FH) C. General RAM, register banks, then SFRs D. Register banks (00H-0FH), bit area (10H-1FH), general RAM (20H-7FH) Answer: B. The 8051 has four register banks at 00H-1FH, 16 bit-addressable bytes at 20H-2FH, and 80 general-purpose bytes at 30H-7FH. (Key point: Internal RAM layout) 2. Which bits select the active register bank? A. RS1 and RS0 of PSW B. TR1 and TR0 of TCON C. SP bits D. EA and ES of IE Answer: A. RS1 and RS0 in the PSW choose among banks 0-3; bank 0 is the default after reset. (Key point: Register bank selection) 3. How many individually addressable bits does the bit-addressable RAM (20H-2FH) provide? A. 64 B. 256 C. 128 D. 80 Answer: C. 16 bytes x 8 bits = 128 bits, with bit addresses 00H-7FH. (Key point: Bit-addressable area) 4. After reset SP = 07H. Where does the first pushed byte go, and what is the consequence? A. At 07H, overwriting R7 of bank 0 B. At 08H, overlapping register banks 1-3 unless SP is changed C. At 30H, in general RAM D. At 80H, in the SFR area Answer: B. SP is incremented before a push, so the stack starts at 08H, overlapping banks 1-3 unless SP is moved. (Key point: Stack after reset) ## Related in Embedded System - [Microcontroller vs microprocessor; 8051 features](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Amicro-vs-microprocessor-8051-features) — Embedded System, chapter 9, asked 2× - [Microprocessor vs microcontroller; 8051 addressing](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-addressing-modes-micro-vs-processor) — Embedded System, chapter 9 - [Addressing modes of 8051](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-addressing-modes) — Embedded System, chapter 9, asked 4× - [Why 8051 / its operational features](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Awhy-8051-features) — Embedded System, chapter 9, asked 2× - [Purpose of port 3 and port 2 of 8051](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-port3-port2-purpose) — Embedded System, chapter 9, asked 2× - [8051 internal structure and family chart](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-internal-structure-family) — Embedded System, chapter 9 ## Related in other subjects - [Bus organization and memory capacity](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Abus-organization-memory-capacity) — Microprocessor, chapter 1 - [Organization of control memory](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acontrol-memory-org) — Computer Organization and Architecture, chapter 3 - [Multiprocessor classification by memory organization](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Amultiprocessor-classification) — Computer Organization and Architecture, chapter 8 - [Selecting a processor or microcontroller](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Aprocessor-selection) — Instrumentation II, chapter 1, asked 4×