--- title: "8051 internal structure and family chart" subject: "Embedded System" chapter: 9 key: "semester_6/embedded_system:8051-internal-structure-family" source: https://www.bctengineer.com/q/semester_6/embedded_system/8051-internal-structure-family site: BCT Engineering --- # 8051 internal structure and family chart Embedded System · Chapter 9: Microcontrollers in Embedded Systems - Asked in: 2070 Bhadra, 4+4 marks - Video: [Block Diagram of 8051 Microcontroller: Architecture and Key Components Explained](https://www.youtube.com/watch?v=I_qFGUTBYek) — Engineering Funda - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/8051-internal-structure-family - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9 ## Question Show the internal structure of the 8051 microcontroller. Provide a comparison chart of the 8051 family members. ## Answer #### Internal structure of the 8051 ```text +------------------------------------------------------+ | Interrupt control +----------+ On-chip | | (INT0,INT1,T0,T1, | 4K ROM | oscillator | | serial) | (code) | and clock | | +----------+ | | +--------+ +-----+ +----------+ +----------------+ | | | CPU: | | PC | | 128 B RAM| | Timer 0, 1 | | | | ALU, | |DPTR | | + SFRs | | Serial port | | | | A, B, | | SP | +----------+ | (UART) | | | | PSW | +-----+ +----------------+ | | +--------+ internal bus | | +------+ +------+ +------+ +------+ +-------------+ | | | P0 | | P1 | | P2 | | P3 | | Bus control | | | +--+---+ +--+---+ +--+---+ +--+---+ +-------------+ | +-----|--------|--------|--------|----------------------+ v v v v Port pins P0.0-P0.7 ... P3.0-P3.7 (32 I/O lines) ``` - **CPU:** 8-bit ALU, accumulator A, register B, PSW (flags), registers R0-R7 (4 banks), PC, DPTR, stack pointer. - **Memory:** 4 KB on-chip ROM and 128 B RAM, plus SFRs. - **Timers/counters:** two 16-bit (T0, T1). **Serial port:** one full-duplex UART. - **Interrupt logic:** five sources with two priority levels. - **I/O ports:** P0-P3, 32 lines; P0 and P2 also carry the address/data bus for external memory. - **Oscillator and bus control:** XTAL1/XTAL2, ALE, PSEN, EA, RST. #### 8051 family comparison | Device | On-chip program memory | RAM | Timers | Interrupts | I/O lines | |---|---|---|---|---|---| | 8031 | none (external ROM) | 128 B | 2 | 5 | 32 | | 8051 | 4 KB ROM (mask) | 128 B | 2 | 5 | 32 | | 8751 | 4 KB EPROM | 128 B | 2 | 5 | 32 | | AT89C51 | 4 KB Flash | 128 B | 2 | 5 | 32 | | 8032 | none | 256 B | 3 | 6 | 32 | | 8052 | 8 KB ROM | 256 B | 3 | 6 | 32 | | 8752 | 8 KB EPROM | 256 B | 3 | 6 | 32 | | AT89C52 | 8 KB Flash | 256 B | 3 | 6 | 32 | | AT89C2051 | 2 KB Flash | 128 B | 2 | 5 | 15 (20-pin) | The 52 series adds Timer 2 and 128 more bytes of RAM; flash versions can be reprogrammed electrically. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. Which set lists major blocks of the 8051? A. CPU only B. CPU, 4 KB ROM, 128 B RAM, timers, UART, interrupt logic, ports C. GPU, DRAM, USB D. ADC and DAC only Answer: B. The 8051 integrates the CPU, memory, timers, serial port, interrupt control and I/O ports. (Key point: Internal blocks) 2. How does the 8031 differ from the 8051? A. It has 8 KB ROM B. It has 3 timers C. It has no on-chip program memory D. It has 64 I/O lines Answer: C. The 8031 needs external ROM. (Key point: 8031 difference) 3. What does the 52 series (8052, AT89C52) add? A. A second UART B. Fewer I/O lines C. Only flash D. Timer 2 and 256 B RAM with 8 KB program memory Answer: D. The 52 series has a third timer, 256 B RAM and 8 KB program memory. (Key point: 52 series) 4. What advantage does AT89C51 flash have over 8051 mask ROM? A. It can be reprogrammed electrically B. It has more RAM C. It has more timers D. It has more pins Answer: A. Flash can be erased and reprogrammed, while mask ROM is fixed at the factory. (Key point: Memory types) 5. Which ports also carry the address/data bus for external memory? A. P1 and P3 B. P2 and P3 C. P0 and P2 D. P1 and P2 Answer: C. P0 and P2 carry the address and data lines. (Key point: Port role) ## Related in Embedded System - [Microcontroller vs microprocessor; 8051 features](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Amicro-vs-microprocessor-8051-features) — Embedded System, chapter 9, asked 2× - [Microprocessor vs microcontroller; 8051 addressing](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-addressing-modes-micro-vs-processor) — Embedded System, chapter 9 - [Addressing modes of 8051](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-addressing-modes) — Embedded System, chapter 9, asked 4× - [Why 8051 / its operational features](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Awhy-8051-features) — Embedded System, chapter 9, asked 2× - [Purpose of port 3 and port 2 of 8051](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-port3-port2-purpose) — Embedded System, chapter 9, asked 2× - [8051 data memory organization](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3A8051-data-memory-organization) — Embedded System, chapter 9 ## Related in other subjects - [Sending structure members to a function](https://www.bctengineer.com/question.md?key=semester_1%2Fcomputer_programming%3Astructure-members-to-function) — Computer Programming, chapter 8 - [Flowchart vs structure chart](https://www.bctengineer.com/question.md?key=semester_6%2Fobject_oriented_analysis_and_design%3Aflowchart-vs-structure-chart) — Object Oriented Analysis and Design, chapter 1 - [Internal structure of the earth](https://www.bctengineer.com/question.md?key=semester_3%2Fengineering_geology_i%3Ainternal-structure-of-the-earth) — Engineering Geology I, chapter 2, asked 7× - [Internal structure of earth and basis of study](https://www.bctengineer.com/question.md?key=semester_3%2Fengineering_geology_i%3Ainternal-structure-of-earth-and) — Engineering Geology I, chapter 2