--- title: "8051 minimum circuit and 75% duty pulse" subject: "Embedded System" chapter: 9 key: "semester_6/embedded_system:8051-min-config-pwm-75" source: https://www.bctengineer.com/q/semester_6/embedded_system/8051-min-config-pwm-75 site: BCT Engineering --- # 8051 minimum circuit and 75% duty pulse Embedded System · Chapter 9: Microcontrollers in Embedded Systems - Asked in: 2074 Bhadra, 4+4 marks - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/8051-min-config-pwm-75 - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-9 ## Question Draw the circuit diagram of the minimum configuration for 8051 microcontroller to operate. Also show the connection of LED at P1.7 and switch at P1.1 in the same circuit. Using an Assembly language, generate a pulse of 75% duty cycle at pin P1.7 when the switch at P1.1 is ON. ## Short answer Minimum circuit: +5V, GND, 12 MHz crystal with 33pF caps, reset using 10µF capacitor and 8.2k resistor, EA to VCC. Connect LED on P1.7 via 330Ω resistor, switch on P1.1 to GND. Program: when switch closed, set P1.7 high for 3 ms and low for 1 ms using delay loops, generating 75% duty cycle at 250 Hz. ## Answer #### Minimum configuration circuit The 8051 needs power, a clock and a reset to run; with internal ROM in use (EA = VCC) no other chip is needed. ```text Power: +5V -> pin 40 (VCC), pin 31 (EA); GND -> pin 20 Reset: +5V --| |--+-- pin 9 (RST) 10uF | [8.2k] | GND Clock: pin 19 --+-- 12 MHz crystal --+-- pin 18 | | 33pF 33pF | | GND GND LED: pin 8 (P1.7) --[330R]--|>|-- GND Switch: pin 2 (P1.1) ---/ --- GND (open=1, closed=0) ``` - **Power:** +5 V at pin 40, GND at pin 20; EA (pin 31) is tied to +5 V to use the internal program memory. - **Clock:** a 12 MHz crystal between pins 18 and 19, with two 33 pF capacitors to ground. - **Reset:** a 10 uF capacitor from +5 V to RST (pin 9) and an 8.2 k resistor from RST to ground give a power-on reset (a push button is optional). - **LED:** P1.7 drives an LED through a 330 ohm resistor to ground (LED on when P1.7 = 1). Port pins can source only a small current through their internal pull-ups, so in practice the LED is often wired from +5 V through the resistor to P1.7 (lit when P1.7 = 0) or driven through a transistor. - **Switch:** between P1.1 and ground. Port 1 has internal pull-ups, so P1.1 = 1 when the switch is open and 0 when it is ON (closed). #### 75 % duty pulse program The period is 4 ms (250 Hz): P1.7 is high for 3 ms and low for 1 ms, repeated while the switch is ON (P1.1 = 0). ```asm ORG 0000H SETB P1.1 ; make P1.1 an input (switch) LOOP: JB P1.1,OFF ; P1.1 = 1 -> switch open (OFF), no pulse SETB P1.7 ; LED pin high ... start of 3 ms HIGH time ACALL D1MS ACALL D1MS ACALL D1MS CLR P1.7 ; LED pin low ... 1 ms LOW time ACALL D1MS SJMP LOOP ; period 4 ms (250 Hz), duty 3/4 = 75 % OFF: CLR P1.7 ; keep LED off while the switch is open SJMP LOOP ; 1 ms delay at 12 MHz: 2 (ACALL) + 1 + 5 x (1 + 98 x 2 + 2) + 2 (RET) = 1000 cycles D1MS: MOV R7,#5 D1: MOV R6,#98 D2: DJNZ R6,D2 DJNZ R7,D1 RET END ``` D1MS takes exactly 1000 machine cycles at 12 MHz (2 + 1 + 5 x 199 + 2). In a simulator, P1.7 was high for 3.001 ms and low for 1.005 ms (duty 74.9 %). If the switch is open (P1.1 = 1), the LED pin stays low. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What does the 8051 need to run with internal ROM? A. Power (EA to VCC), a clock and a reset B. An external RAM and ROM C. A UART D. A latch Answer: A. Power, a crystal clock and a reset circuit are enough; EA is tied to +5 V for internal program memory. (Key point: Minimum configuration) 2. Why is P1.1 = 0 when the switch to ground is closed? A. Port 1 pins are outputs by default B. P1.1 is pulled up internally, so open = 1 and closed = 0 C. The LED pulls it low D. EA is grounded Answer: B. Internal pull-ups hold the pin at 1 when open; closing the switch grounds it. (Key point: Switch input) 3. For a 4 ms period with 75 % duty, how long is P1.7 high and low? A. 1 ms high, 3 ms low B. 2 ms high, 2 ms low C. 3 ms high, 1 ms low D. 3 ms high, 3 ms low Answer: C. 75 % of 4 ms is 3 ms high, leaving 1 ms low. (Key point: Duty cycle timing) 4. How does the program get 3 ms high time? A. Calls the 1 ms delay D1MS three times after SETB P1.7 B. Calls D1MS once C. Uses Timer 1 only D. Uses CPL Answer: A. Three ACALL D1MS instructions after SETB P1.7, then CLR P1.7 and one more D1MS. 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