---
title: "Associative cache mapping"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:associative-cache-mapping"
source: https://www.bctengineer.com/q/semester_6/embedded_system/associative-cache-mapping
site: BCT Engineering
---

# Associative cache mapping

Embedded System · Chapter 4: Memory

- Asked in: 2072 Asoj, 5 marks; 2074 Bhadra, 5 marks (asked 2 times)
- Video: [L-3.8: Fully Associative Mapping with examples in Hindi | Cache Mapping | Computer Organisation](https://www.youtube.com/watch?v=sLCJJdz0WAg) — Gate Smashers
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/associative-cache-mapping
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Explain associative cache mapping technique (with its merits and demerits).

## Short answer

Fully associative mapping allows any main memory block to be placed in any cache line. Address has tag and offset; tag compared with all lines simultaneously. Merits: no conflict misses, highest hit ratio. Demerits: expensive due to one comparator per line, slower, requires replacement policy, and feasible only for small caches.

## Answer

In **associative (fully associative) mapping**, a main-memory block can be placed in **any** line of the cache. The memory address is divided into a **tag** (the block number) and an **offset** (word within the block). There is no index field.

```text
 Address:  | Tag (block no.) | Offset |
              |
      compare in parallel with every line's tag
 +------+-----+------+   +------+
 | tag0 | data|valid |-> |  =?  |--+
 | tag1 | data|valid |-> |  =?  |--+--> hit / select line
 | ...                                 |
 +------------------+                  v
                                      data
```
**Operation:** the CPU sends the address; the tag is compared with the tags of all lines at the same time (using content-addressable memory). If one matches (and valid), it is a hit and the offset selects the word. Otherwise it is a miss: the block is fetched from main memory and put into any free line, or, if the cache is full, a replacement algorithm (LRU, FIFO, random) chooses a line to evict.

#### Merits
- Most flexible placement, so there are no conflict misses and the highest hit ratio for a given size.
- Cache space is fully used.

#### Demerits
- Needs a comparator for every line, making it costly and complex.
- Slower search and higher power use.
- Needs a replacement algorithm.
- Practical only for small caches (e.g. TLB).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Where can a block be placed in associative mapping?
   A. One fixed line
   B. One fixed set only
   C. Only the first line
   D. Any cache line
   Answer: D. Address is tag + offset with no index. (Key point: Placement)

2. How is a hit detected?
   A. Tag compared with all valid line tags in parallel
   B. Index selects one line
   C. Sequential search of main memory
   D. By offset alone
   Answer: A. Content-addressable memory does the parallel compare. (Key point: Lookup)

3. Which is a merit?
   A. Low cost
   B. No conflict misses and highest hit ratio
   C. No replacement needed
   D. Fast simple search
   Answer: B. Cache space is fully used. (Key point: Merit)

4. What happens on a miss with a full cache?
   A. Data is discarded
   B. The CPU halts
   C. A replacement algorithm such as LRU or FIFO chooses a line to evict
   D. Mapping index chooses the line
   Answer: C. The block is fetched from main memory into the chosen line. (Key point: Miss when full)

## Related in Embedded System

- [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3×

## Related in other subjects

- [Cache read and direct-mapping demerits](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-demerits) — Computer Organization and Architecture, chapter 6
- [Associative cache mapping with example](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-cache-example) — Computer Organization and Architecture, chapter 6
- [Associative mapping technique](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Aassoc-mapping-explain) — Computer Organization and Architecture, chapter 6
- [Direct cache mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping) — Computer Organization and Architecture, chapter 6, asked 3×