--- title: "Cache memory mapping techniques" subject: "Embedded System" chapter: 4 key: "semester_6/embedded_system:cache-mapping-techniques" source: https://www.bctengineer.com/q/semester_6/embedded_system/cache-mapping-techniques site: BCT Engineering --- # Cache memory mapping techniques Embedded System · Chapter 4: Memory - Asked in: 2071 Bhadra, 2+6 marks; 2073 Magh, 8 marks; 2079 Jestha, 3+5 marks (asked 3 times) - Video: [L-3.5: What is Cache Mapping || Cache Mapping techniques || Computer Organisation and Architecture](https://www.youtube.com/watch?v=m1dA7D6c3C0) — Gate Smashers - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/cache-mapping-techniques - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4 ## Question What is cache memory? What are the basic techniques for cache mapping? How do direct mapping and fully associative mapping differ? ## Short answer Cache memory provides fast storage for frequently accessed data. Mapping techniques: direct (fixed line by index), fully associative (any line, tag compared in parallel), set-associative (block to a set, placed in any way). Direct mapping is simple and cheap but has conflict misses; fully associative gives highest hit rate with costly parallel comparators. ## Answer **Cache memory** is a small, fast memory placed between the processor and the main memory that holds copies of frequently used data/instructions, using the principle of locality. A hit gives data in one cache access; a miss goes to main memory. Because the cache is much smaller than main memory, a rule is needed to decide where each memory block may be placed. This rule is the **mapping technique**. Memory address splits into **tag | index | offset**. The offset selects the byte within a block, the index selects the cache line or set, and the tag identifies which memory block is stored there. #### Basic mapping techniques 1. **Direct mapping:** each main-memory block can go into exactly one cache line: line = (block address) mod (number of lines). 2. **Fully associative mapping:** a block can be placed in any cache line. The tag is the whole block address, compared with all line tags in parallel. 3. **Set-associative mapping:** the cache is divided into sets. A block maps to one set and can be in any line (way) of that set, e.g. 2-way or 4-way. ```text Direct: address = | tag | index | offset | index -> one line -> compare 1 tag Assoc.: address = | tag (block no.) | offset | compare tag with ALL lines at once ``` #### Direct versus fully associative mapping | Point | Direct mapping | Fully associative | |---|---|---| | Placement | Only one possible line | Any line | | Address fields | tag, index, offset | tag, offset (no index) | | Comparators | 1 | One per line (all in parallel) | | Hardware cost | Low, simple | High, expensive (CAM) | | Hit time | Fast | Slower, more complex search | | Conflict misses | High (two hot blocks may fight for one line) | None (only capacity misses) | | Replacement policy | Not needed | Needed (LRU, FIFO, random) | | Hit ratio | Lower | Highest | | Use | Large caches | Small caches, TLBs | ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is cache memory? A. Large slow memory B. Secondary storage C. Small fast memory between processor and main memory holding frequently used data D. A register file Answer: C. It uses the principle of locality. (Key point: Cache) 2. Which fields does a direct-mapped address have? A. tag, offset B. index, offset C. tag only D. tag, index, offset Answer: D. Fully associative has no index field. (Key point: Address fields) 3. Where can a block go in direct mapping? A. Exactly one line: block mod number of lines B. Any line C. Any line of a set D. Nowhere Answer: A. This single choice causes conflict misses. (Key point: Direct placement) 4. Which is true of fully associative compared to direct? A. Needs only one comparator B. No conflict misses but needs a comparator per line and a replacement policy C. Needs no replacement policy D. Cheaper hardware Answer: B. Hardware is costly (CAM), so it is used for small caches such as TLBs. (Key point: Associative vs direct) ## Related in Embedded System - [Associative cache mapping](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aassociative-cache-mapping) — Embedded System, chapter 4, asked 2× - [Cache write techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-write-techniques) — Embedded System, chapter 4 - [Which cache is better (4KB vs 12KB)](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-comparison-4kb-12kb) — Embedded System, chapter 4, asked 2× - [Which cache is better (2KB vs 8KB)](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-comparison-2kb-8kb) — Embedded System, chapter 4, asked 2× - [Cache write policy and replacement algorithm](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-write-policy-replacement) — Embedded System, chapter 4 ## Related in other subjects - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3× - [Cache mapping techniques](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Acache-mapping-techniques) — Computer Organization and Architecture, chapter 6, asked 7× - [Cache management; direct vs associative address structure](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-vs-assoc-address) — Computer Organization and Architecture, chapter 6 - [Write policy; direct vs associative mapping](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Awp-direct-vs-assoc) — Computer Organization and Architecture, chapter 6