---
title: "CMOS NAND, NOR (and NOT) circuits"
subject: "Embedded System"
chapter: 8
key: "semester_6/embedded_system:cmos-nand-nor-circuits"
source: https://www.bctengineer.com/q/semester_6/embedded_system/cmos-nand-nor-circuits
site: BCT Engineering
---

# CMOS NAND, NOR (and NOT) circuits

Embedded System · Chapter 8: IC Technology

- Asked in: 2079 Asoj, 5 marks; 2078 Baisakh, 5 marks (asked 2 times)
- Video: [Lec 14b: CMOS Gates](https://www.youtube.com/watch?v=B1S5tgIJ1Fg) — Embedded Systems
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/cmos-nand-nor-circuits
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-8

## Question

Draw the MOS (CMOS) circuit diagrams for NAND, NOR and NOT gates, explain their operation and derive their truth tables.

## Short answer

CMOS NAND uses parallel PMOS and series NMOS; output low only when both inputs high. NOR uses series PMOS and parallel NMOS; output high only when both inputs low. NOT (invert) has one PMOS and one NMOS; output is inverse of input.

## Answer

CMOS gates use a **pull-up network of PMOS** transistors to VDD and a **pull-down network of NMOS** transistors to ground. A PMOS conducts when its gate is 0, an NMOS when its gate is 1. Exactly one network conducts for each input, so there is no static current.

#### NOT gate (inverter)

```text
        VDD
         |
     |--+ PMOS
 A --|    |
     |--+-+------ Y
     |--+ |
 A --|    NMOS
     |--+
         |
        GND
```

- A = 0: PMOS on, NMOS off, so Y = 1.
- A = 1: PMOS off, NMOS on, so Y = 0.

| A | Y |
|---|---|
| 0 | 1 |
| 1 | 0 |

#### NAND gate

```text
         VDD
       +--+--+
    P1 |     | P2        P1, P2 in parallel
 A -|<     B -|<
       +--+--+
          |
          +--------- Y
          |
       N1 | (A)       N1, N2 in series
          |
       N2 | (B)
          |
         GND
```

Y is pulled to 0 only when both NMOS are on (A = 1 and B = 1); otherwise at least one PMOS is on.

| A | B | P1 | P2 | N1 | N2 | Y = (A·B)' |
|---|---|---|---|---|---|---|
| 0 | 0 | on | on | off | off | 1 |
| 0 | 1 | on | off | off | on | 1 |
| 1 | 0 | off | on | on | off | 1 |
| 1 | 1 | off | off | on | on | 0 |

#### NOR gate

```text
         VDD
          |
       P1 | (A)       P1, P2 in series
          |
       P2 | (B)
          |
          +--------- Y
       +--+--+
    N1 |     | N2        N1, N2 in parallel
       +--+--+
         GND
```

Y is pulled to 1 only when both PMOS are on (A = 0 and B = 0); if any input is 1 an NMOS pulls Y to 0.

| A | B | P1 | P2 | N1 | N2 | Y = (A+B)' |
|---|---|---|---|---|---|---|
| 0 | 0 | on | on | off | off | 1 |
| 0 | 1 | on | off | off | on | 0 |
| 1 | 0 | off | on | on | off | 0 |
| 1 | 1 | off | off | on | on | 0 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. CMOS gate structure?
   A. NMOS up, PMOS down
   B. All NMOS
   C. PMOS pull-up to VDD and NMOS pull-down to ground
   D. All PMOS
   Answer: C. One network conducts. (Key point: Networks)

2. NAND pull-down?
   A. Parallel
   B. Two NMOS in series
   C. Single PMOS
   D. Series PMOS
   Answer: B. Low only if A=B=1. (Key point: NAND)

3. NOR pull-up?
   A. Two PMOS in series
   B. Parallel PMOS
   C. Series NMOS
   D. Parallel NMOS
   Answer: A. High only if A=B=0. (Key point: NOR)

4. Why no static current?
   A. Both on
   B. Resistor limits
   C. Supply off
   D. Only one network conducts at a time
   Answer: D. Complementary. (Key point: Static current)

## Related in Embedded System

- [Semi-custom ASIC and manufacturing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Asemi-custom-asic-types-manufacturing) — Embedded System, chapter 8

## Related in other subjects

- [Encoder; NAND and XOR truth tables](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Aencoder-truth-tables) — Basic Electronics Engineering, chapter 6
- [Why NOR and NAND are universal gates](https://www.bctengineer.com/question.md?key=semester_2%2Fbasic_electronics_engineering%3Auniversal-gates-nor-nand) — Basic Electronics Engineering, chapter 6
- [Why NAND and NOR are universal gates](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Auniversal-gates-why) — Digital Logic, chapter 2
- [CMOS characteristics; 2-input CMOS NOR](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Acmos-characteristics-nor-2input) — Digital Logic, chapter 10