---
title: "Compose 2^(k+1) x m from 2^k x m"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-2k1m-from-2km"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2k1m-from-2km
site: BCT Engineering
---

# Compose 2^(k+1) x m from 2^k x m

Embedded System · Chapter 4: Memory

- Asked in: 2070 Magh, 3 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2k1m-from-2km
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Compose 2^(k+1) × m memory using 2^k × m memories.

## Short answer

Use two 2^k x m modules and (k+1) address lines. Connect A(k-1)..A0 to both in parallel. A_k selects module: A_k=0 enables M0, A_k=1 enables M1. Data lines are tied together via tri-state outputs.

## Answer

Let the base module be 2^k x m (k address lines, m data lines, chip select CS). The target has twice as many words of the same width, so it needs **two modules** and **k + 1 address lines**.

#### Method
- The width stays m bits, so no width expansion is needed.
- The low-order k address lines A(k-1)..A0 go to both modules in parallel.
- The extra high-order line A_k selects the module: A_k = 0 enables M0 (words 0 to 2^k - 1) and A_k = 1 enables M1 (words 2^k to 2^(k+1) - 1). A 1-to-2 decoder does this (a NOT gate for M0 and a direct connection for M1).
- The data lines D(m-1)..D0 of the modules are tied together because the outputs are tri-state; only the enabled module drives the bus.

```text
 A(k-1)..A0 ------+------------+
                  |            |
 A_k --[NOT]--> CS [ M0 ]  CS [ M1 ] <-- A_k
                 2^k x m     2^k x m
                    \          /
                  D(m-1)..D0 (shared)
```
| A_k | Module enabled | Address range |
|---|---|---|
| 0 | M0 | 0 to 2^k - 1 |
| 1 | M1 | 2^k to 2^(k+1) - 1 |

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 2^k x m modules make a 2^(k+1) x m memory?
   A. 2
   B. 4
   C. k+1
   D. m
   Answer: A. Twice the words at the same width needs two modules. (Key point: Number of modules)

2. Which address line selects between the two modules?
   A. The extra high-order line A_k
   B. A0
   C. The data lines
   D. Read/write
   Answer: A. A_k = 0 enables M0 and A_k = 1 enables M1; low-order lines go to both modules. (Key point: Module selection)

3. Why can the data lines of both modules be tied together?
   A. Outputs are tri-state and only the enabled module drives the bus
   B. They hold identical data
   C. Only M0 is ever read
   D. A multiplexer merges them
   Answer: A. Tri-state outputs let only the enabled module drive the shared bus. (Key point: Shared data lines)

## Related in Embedded System

- [Compose 2^(k+1) x 2n from 2^k x n](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2k1x2n) — Embedded System, chapter 4