---
title: "Construct 2^(k+1) x n and 2^k x 4n"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-2k1n-and-2k4n"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2k1n-and-2k4n
site: BCT Engineering
---

# Construct 2^(k+1) x n and 2^k x 4n

Embedded System · Chapter 4: Memory

- Asked in: 2073 Bhadra, 4+4 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2k1n-and-2k4n
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Construct 2^(k+1) × n and 2^k × 4n memories using 2^k × n memory modules.

## Short answer

(a) Depth expansion for 2^(k+1)×n: two 2^k×n modules, A_k selects module via decoder. (b) Width expansion for 2^k×4n: four 2^k×n modules in parallel share address/control lines; each provides n bits to form 4n-bit word.

## Answer

Let the base module be 2^k x n (k address lines, n data lines, enable/chip-select CS, read/write).

#### (a) 2^(k+1) x n: double the depth (2 modules)
The word width is the same (n) but twice the words are needed, so the address has k + 1 bits.
- Two modules, M0 and M1, receive address lines A(k-1)..A0 in parallel.
- The extra high-order address bit A_k selects the module through a 1-to-2 decoder (A_k itself goes to CS of M1 and its inverse to CS of M0).
- Data lines D(n-1)..D0 of both modules are tied together (tri-state outputs, only the enabled one drives the bus).

```text
 A(k-1)..A0 ------------+------------+
                        |            |
 A_k --+--[NOT]--> CS [ M0 ]    CS [ M1 ] <-- A_k
                       2^k x n    2^k x n
                          \          /
                      D(n-1)..D0 (shared)
```
| A_k | Module | Addresses |
|---|---|---|
| 0 | M0 | 0 to 2^k - 1 |
| 1 | M1 | 2^k to 2^(k+1) - 1 |

#### (b) 2^k x 4n: increase the width by 4 (4 modules)
The number of words is the same (2^k) but each word must be 4n bits, so four modules are placed side by side.
- All four modules share address lines A(k-1)..A0, CS and read/write lines.
- Each module supplies n bits: M0 gives D(n-1)..D0, M1 gives D(2n-1)..Dn, M2 gives D(3n-1)..D2n, M3 gives D(4n-1)..D3n.
- No decoder is needed.

```text
 A(k-1)..A0, CS, R/W ----+--------+--------+--------+
                        [M0]     [M1]     [M2]     [M3]
                          |        |        |        |
                     D(n-1)..0  D(2n-1)..n D(3n-1)..2n D(4n-1)..3n
                         \-------- 4n-bit data bus --------/
```

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. For 2^(k+1) x n from 2^k x n modules, what is done?
   A. Two modules with the extra address bit A_k selecting one
   B. Four modules side by side
   C. One module with doubled data lines
   D. Modules in series with no select
   Answer: A. The word width is unchanged, so two modules are enabled alternately by A_k. (Key point: Depth expansion)

2. How many 2^k x n modules are needed for 2^k x 4n?
   A. 4
   B. 2
   C. 8
   D. 16
   Answer: A. Same number of words but 4 times the width needs four modules side by side. (Key point: Width expansion modules)

3. In the 2^k x 4n memory, how are the modules connected?
   A. Share address, CS and R/W; each gives n bits of the word; no decoder
   B. Each has own address; decoder selects one
   C. Only one is enabled at a time
   D. Data lines are tied together
   Answer: A. Each module supplies n bits of the 4n-bit word and all are accessed together, so no decoder is needed. (Key point: Width expansion wiring)

4. How many address lines does the 2^(k+1) x n memory need?
   A. k + 1
   B. k
   C. 2k
   D. k + 2
   Answer: A. Twice the words needs one extra high-order address bit. (Key point: Address lines)

## Related in Embedded System

- [Write ability and storage permanence](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Awrite-ability-storage-permanence) — Embedded System, chapter 4, asked 5×
- [Compose 2^(k+1) x m from 2^k x m](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2k1m-from-2km) — Embedded System, chapter 4