---
title: "Compose 2K x 16 ROM using 1K x 4"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-2kx16-from-1kx4"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2kx16-from-1kx4
site: BCT Engineering
---

# Compose 2K x 16 ROM using 1K x 4

Embedded System · Chapter 4: Memory

- Asked in: 2078 Baisakh, 5 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2kx16-from-1kx4
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Compose 2K × 16 ROM using 1K × 4 ROMs.

## Short answer

Use 8 1K×4 ROMs. Width: 4 in parallel give 16-bit word (D3..D0, D7..D4, D11..D8, D15..D12). Depth: A10 to a 1-to-2 decoder selects one of two rows. A9..A0 to all. Outputs share tri-state bus. Result: 2K×16 ROM.

## Answer

**Given:** base module 1K x 4 ROM; **required:** 2K x 16 ROM. Number of modules = (depth ratio) x (width ratio) = 2 x 4 = **8**.

#### Method
- **Width:** the required word is 16 bits and each module gives 4 bits, so 4 modules are placed side by side (same address and enable); their data outputs are combined to form the full word.
- **Depth:** twice as many words are needed, so 2 rows of modules are used. The extra high-order address line **A10** goes to a 1-to-2 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
- Total address lines = 10 + 1 = 11; total data lines = 16.

#### Block diagram
```text
 Address bits: 11 lines
   A10 --> [1-to-2 decoder] --> row enables E0, E1
   A9..A0 --> to every module (parallel)

 row 0: [M00] [M01] [M02] [M03]  <- E0
 row 1: [M10] [M11] [M12] [M13]  <- E1

 Data: M*0: D3..D0, M*1: D7..D4, M*2: D11..D8, M*3: D15..D12
```

#### Address ranges (row selected by the high bit)
| A10 | Row enabled | Address range |
|---|---|---|
| 0 | Row 0 (E0) | 000-3FFH |
| 1 | Row 1 (E1) | 400-7FFH |

Each row holds four 1K x 4 ROMs, which together supply D15..D0.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 1K x 4 ROMs form a 2K x 16 ROM?
   A. 8
   B. 4
   C. 2
   D. 16
   Answer: A. Depth ratio 2 x width ratio 4 = 8. (Key point: Number of modules)

2. Why are four ROMs placed side by side in each row?
   A. Each gives 4 bits, so four make a 16-bit word
   B. To increase the number of words
   C. To save address lines
   D. To give redundancy
   Answer: A. 16 bits / 4 bits per module = 4 modules per row. (Key point: Width expansion)

3. What enables one row at a time?
   A. A10 through a 1-to-2 decoder
   B. A11 A10 through a 2-to-4 decoder
   C. The data lines
   D. A0
   Answer: A. Two rows need one extra bit A10; A9..A0 go to every ROM. (Key point: Row selection)

## Related in Embedded System

- [Compose 1K x 8 ROMs into 2K x 16](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx8) — Embedded System, chapter 4, asked 2×
- [Compose 1K x 8 ROMs into 4K x 8 ROM](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx8-from-1kx8) — Embedded System, chapter 4, asked 2×
- [Compose 4K x 16 ROM using 1K x 8](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx16-from-1kx8) — Embedded System, chapter 4