---
title: "Compose 1K x 8 ROMs into 2K x 16"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-2kx16-from-1kx8"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2kx16-from-1kx8
site: BCT Engineering
---

# Compose 1K x 8 ROMs into 2K x 16

Embedded System · Chapter 4: Memory

- Asked in: 2072 Magh, 5 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-2kx16-from-1kx8
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Compose 1K × 8 ROMs into a 2K × 16 ROM.

## Short answer

Use 4 modules. For width, pair two modules side by side to get 16-bit data. For depth, A10 drives a 1-to-2 decoder enabling one of two rows. A9..A0 parallel to all. Data outputs D7..D0 and D15..D8 share bus. Final: 2K×16 ROM.

## Answer

**Given:** base module 1K x 8 ROM; **required:** 2K x 16 ROM. Number of modules = (depth ratio) x (width ratio) = 2 x 2 = **4**.

#### Method
- **Width:** the required word is 16 bits and each module gives 8 bits, so 2 modules are placed side by side (same address and enable); their data outputs are combined to form the full word.
- **Depth:** twice as many words are needed, so 2 rows of modules are used. The extra high-order address line **A10** goes to a 1-to-2 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
- Total address lines = 10 + 1 = 11; total data lines = 16.

#### Block diagram
```text
 Address bits: 11 lines
   A10 --> [1-to-2 decoder] --> row enables E0, E1
   A9..A0 --> to every module (parallel)

 row 0: [M00] [M01]  <- E0
 row 1: [M10] [M11]  <- E1

 Data: M*0: D7..D0, M*1: D15..D8
```

#### Address ranges (row selected by the high bit)
| A10 | Row enabled | Address range |
|---|---|---|
| 0 | Row 0 (E0) | 000-3FFH |
| 1 | Row 1 (E1) | 400-7FFH |

In each row, ROM M*0 gives the low byte D7..D0 and ROM M*1 gives the high byte D15..D8.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 1K x 8 ROMs form a 2K x 16 ROM?
   A. 4
   B. 2
   C. 8
   D. 16
   Answer: A. Depth 2 x width 2 = 4 modules. (Key point: Number of modules)

2. How are the four ROMs arranged?
   A. 2 rows of 2 ROMs: side by side for width, rows selected by A10
   B. 4 ROMs in one row
   C. 4 rows selected by A11A10
   D. 2 rows selected by A9
   Answer: A. Two ROMs side by side give 16 bits; A10 chooses between two rows. (Key point: Width and depth)

3. How many address lines in total are needed?
   A. 11
   B. 10
   C. 12
   D. 16
   Answer: A. 2K = 2^11 giving 10 + 1 = 11 lines. (Key point: Address lines)

4. What are the address ranges of the two rows?
   A. 000-3FFH and 400-7FFH
   B. 000-7FFH and 800-FFFH
   C. 000-1FFH and 200-3FFH
   D. 000-3FFH and 800-BFFH
   Answer: A. Each row has 1K = 400H words, so row 1 begins at 400H. (Key point: Address ranges)

## Close variants set in other exams

- [Compose 1K x 8 ROMs into 4K x 8 ROM](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx8-from-1kx8) — Embedded System, chapter 4, asked 2×

## Related in Embedded System

- [Compose 2K x 16 ROM using 1K x 4](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx4) — Embedded System, chapter 4
- [Compose 4K x 16 ROM using 1K x 8](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx16-from-1kx8) — Embedded System, chapter 4