---
title: "Compose 4K x 16 ROM using 1K x 8"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-4kx16-from-1kx8"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-4kx16-from-1kx8
site: BCT Engineering
---

# Compose 4K x 16 ROM using 1K x 8

Embedded System · Chapter 4: Memory

- Asked in: 2076 Baisakh, 5 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-4kx16-from-1kx8
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Compose 4K × 16 ROM using 1K × 8 ROMs.

## Short answer

Use 8 modules. Width: two per row form 16 bits. Depth: A11,A10 to a 2-to-4 decoder selects one of four rows. A9..A0 to all. Data outputs share tri-state bus. Addresses: 000-3FFH to C00-FFFH. Result: 4K×16 ROM.

## Answer

**Given:** base module 1K x 8 ROM; **required:** 4K x 16 ROM. Number of modules = (depth ratio) x (width ratio) = 4 x 2 = **8**.

#### Method
- **Width:** the required word is 16 bits and each module gives 8 bits, so 2 modules are placed side by side (same address and enable); their data outputs are combined to form the full word.
- **Depth:** 4 times as many words are needed, so 4 rows of modules are used. The two extra high-order address lines **A11 and A10** go to a 2-to-4 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
- Total address lines = 10 + 2 = 12; total data lines = 16.

#### Block diagram
```text
 Address bits: 12 lines
   A11 A10 --> [2-to-4 decoder] --> row enables E0..E3
   A9..A0 --> to every module (parallel)

 row 0: [M00] [M01]  <- E0
 row 1: [M10] [M11]  <- E1
 row 2: [M20] [M21]  <- E2
 row 3: [M30] [M31]  <- E3

 Data: M*0: D7..D0, M*1: D15..D8
```

#### Address ranges (row selected by the high bits)
| A11 A10 | Row enabled | Address range |
|---|---|---|
| 00 | Row 0 (E0) | 000-3FFH |
| 01 | Row 1 (E1) | 400-7FFH |
| 10 | Row 2 (E2) | 800-BFFH |
| 11 | Row 3 (E3) | C00-FFFH |

In each row, ROM M*0 gives the low byte D7..D0 and ROM M*1 gives the high byte D15..D8.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 1K x 8 ROMs form a 4K x 16 ROM?
   A. 8
   B. 4
   C. 16
   D. 2
   Answer: A. Depth 4 x width 2 = 8 modules. (Key point: Number of modules)

2. Which decoder enables the rows?
   A. 2-to-4 driven by A11 A10
   B. 1-to-2 driven by A10
   C. 3-to-8 driven by A11-A9
   D. None
   Answer: A. Four rows need a 2-to-4 decoder on the two extra high-order bits. (Key point: Decoder)

3. How many address and data lines does it have?
   A. 12 address, 16 data
   B. 10 address, 16 data
   C. 12 address, 8 data
   D. 11 address, 16 data
   Answer: A. 4K needs 12 address lines and the word is 16 bits wide. (Key point: Totals)

4. What address range does row 3 (A11A10 = 11) cover?
   A. C00-FFFH
   B. 800-BFFH
   C. 400-7FFH
   D. 000-3FFH
   Answer: A. A11A10 = 11 gives 3 x 400H = C00H to FFFH. (Key point: Address ranges)

## Related in Embedded System

- [Compose 1K x 8 ROMs into 4K x 8 ROM](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx8-from-1kx8) — Embedded System, chapter 4, asked 2×
- [Compose 1K x 8 ROMs into 2K x 16](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx8) — Embedded System, chapter 4, asked 2×
- [Compose 2K x 16 ROM using 1K x 4](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx4) — Embedded System, chapter 4