---
title: "Compose 1K x 8 ROMs into 4K x 8 ROM"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:compose-4kx8-from-1kx8"
source: https://www.bctengineer.com/q/semester_6/embedded_system/compose-4kx8-from-1kx8
site: BCT Engineering
---

# Compose 1K x 8 ROMs into 4K x 8 ROM

Embedded System · Chapter 4: Memory

- Asked in: 2075 Baisakh, 4 marks
- Video: [MEMORY COMPOSING | All possible cases explained.](https://www.youtube.com/watch?v=yANZkS2p1tU) — Shiva Gyawali
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/compose-4kx8-from-1kx8
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

Compose 1K × 8 ROMs into a 4K × 8 ROM.

## Short answer

Use 4 1K×8 ROMs. A11,A10 feed a 2-to-4 decoder to select one row. A9..A0 connect to all modules in parallel. 8-bit data outputs share a tri-state bus. Result: 4K×8 ROM.

## Answer

**Given:** base module 1K x 8 ROM; **required:** 4K x 8 ROM. Number of modules = (depth ratio) x (width ratio) = 4 x 1 = **4**.

#### Method
- **Width:** the word width is unchanged (8 bits), so no width expansion is needed.
- **Depth:** 4 times as many words are needed, so 4 rows of modules are used. The two extra high-order address lines **A11 and A10** go to a 2-to-4 decoder whose outputs enable one row at a time. The low-order 10 address lines (A9..A0) go to every module in parallel. The rows share the same data lines (tri-state outputs).
- Total address lines = 10 + 2 = 12; total data lines = 8.

#### Block diagram
```text
 Address bits: 12 lines
   A11 A10 --> [2-to-4 decoder] --> row enables E0..E3
   A9..A0 --> to every module (parallel)

 row 0: [M00]  <- E0
 row 1: [M10]  <- E1
 row 2: [M20]  <- E2
 row 3: [M30]  <- E3

 Data: 8 lines (all rows share them)
```

#### Address ranges (row selected by the high bits)
| A11 A10 | Row enabled | Address range |
|---|---|---|
| 00 | Row 0 (E0) | 000-3FFH |
| 01 | Row 1 (E1) | 400-7FFH |
| 10 | Row 2 (E2) | 800-BFFH |
| 11 | Row 3 (E3) | C00-FFFH |

Each 1K x 8 ROM has 10 address lines (A9..A0) and 8 data lines.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How many 1K x 8 ROMs make a 4K x 8 ROM?
   A. 4
   B. 2
   C. 8
   D. 16
   Answer: A. Depth ratio 4, width ratio 1 gives 4 modules. (Key point: Number of modules)

2. Which lines go to the decoder and which decoder?
   A. A11 A10 to a 2-to-4 decoder
   B. A9 A8 to a 2-to-4 decoder
   C. A11 to a 1-to-2 decoder
   D. A11-A9 to a 3-to-8 decoder
   Answer: A. The two extra high-order bits select one of four rows; A9..A0 go to every ROM. (Key point: Decoder)

3. What is the address range of the third ROM (A11A10 = 10)?
   A. 800H-BFFH
   B. 400H-7FFH
   C. 000H-3FFH
   D. C00H-FFFH
   Answer: A. A11A10 = 10 gives 2 x 400H = 800H up to BFFH. (Key point: Address range)

4. How many address lines does the 4K x 8 ROM need?
   A. 12
   B. 10
   C. 11
   D. 8
   Answer: A. 4K = 2^12 so 12 address lines (10 + 2). (Key point: Address lines)

## Close variants set in other exams

- [Compose 1K x 8 ROMs into 2K x 16](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx8) — Embedded System, chapter 4, asked 2×

## Related in Embedded System

- [Compose 4K x 16 ROM using 1K x 8](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx16-from-1kx8) — Embedded System, chapter 4
- [Compose 2K x 16 ROM using 1K x 4](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx4) — Embedded System, chapter 4

## Related in other subjects

- [Interface two 4K x 8 ROM with 3:8 decoder](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-4k-rom-38-decoder) — Microprocessor, chapter 4