--- title: "Control unit sub-operations of GPP" subject: "Embedded System" chapter: 2 key: "semester_6/embedded_system:control-unit-sub-operations" source: https://www.bctengineer.com/q/semester_6/embedded_system/control-unit-sub-operations site: BCT Engineering --- # Control unit sub-operations of GPP Embedded System · Chapter 2: Hardware Design Issues - Asked in: 2071 Bhadra, 6 marks; 2071 Magh, 8 marks; 2078 Baisakh, 6 marks; 2078 Poush, 4 marks (asked 4 times) - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/control-unit-sub-operations - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2 ## Question Explain the control unit sub-operations (basic operations carried out by the controller, with instruction cycles) of a general-purpose processor with a suitable example. ## Short answer The control unit executes the instruction cycle: fetch (IR←Mem[PC], PC++), decode, operand fetch, execute (ALU operation), and store result. For ADD R1, [2000H], it fetches the instruction, reads memory address 2000H, adds to R1, and writes back. Pipelining overlaps these steps to raise throughput. ## Answer The **control unit (controller)** of a GPP repeatedly executes the **instruction cycle**, a sequence of sub-operations (micro-operations) that bring an instruction from memory and carry it out. The basic stages are **fetch, decode, execute and store**. #### Sub-operations 1. **Fetch:** read the instruction from memory. - MAR <- PC (put the address on the bus) - MDR <- Memory[MAR] (read) - IR <- MDR; PC <- PC + 1 2. **Decode:** the control unit decodes the opcode in IR, determining the operation, the operand locations (addressing mode) and the control signals needed. 3. **Fetch operands:** read registers or memory (e.g. MAR <- address field; MDR <- Memory[MAR]). 4. **Execute:** the ALU performs the operation (add, AND, compare, shift, branch condition test). 5. **Store result:** write the result into a register or memory (or update PC for jumps). ```text +-------+ +--------+ +---------+ +-------+ -->| Fetch |-->| Decode |-->| Execute |-->| Store |--+ +-------+ +--------+ +---------+ +-------+ | ^ | +---------------- next instruction -----------+ ``` #### Example: ADD R1, [2000H] (R1 <- R1 + memory[2000H]) | Cycle | Micro-operation | |---|---| | Fetch | MAR <- PC; IR <- Mem[MAR]; PC <- PC + 1 | | Decode | Control unit finds ADD with a direct memory operand | | Operand fetch | MAR <- 2000H; MDR <- Mem[MAR] | | Execute | ALU: R1 + MDR | | Store | R1 <- ALU result; status flags updated | Pipelined processors overlap these sub-operations for several instructions to raise throughput. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What are the basic stages of the instruction cycle? A. Reset, halt, run, stop B. Read, print, scan, save C. Fetch, decode, execute, store D. Compile, link, load, run Answer: C. The control unit repeats fetch, decode, execute and store (with operand fetch as needed). (Key point: Instruction cycle stages) 2. Which sequence correctly shows fetch? A. MAR <- 2000H only B. IR <- ALU; PC <- 0 C. R1 <- R1 + MDR D. MAR <- PC; MDR <- Mem[MAR]; IR <- MDR; PC <- PC + 1 Answer: D. The PC address goes to MAR, memory is read into MDR, then IR; PC increments. (Key point: Fetch micro-operations) 3. What does the control unit determine in decode? A. Operation, operand locations (addressing mode) and needed control signals B. The final result C. Memory size D. Clock frequency Answer: A. Decoding the opcode in IR selects the operation, operand locations and control signals. (Key point: Decode) 4. For ADD R1,[2000H], what happens in operand fetch? A. R1 <- result B. MAR <- 2000H; MDR <- Mem[MAR] C. PC <- 2000H D. IR <- R1 Answer: B. The memory operand at 2000H is read into MDR before the ALU adds it to R1. (Key point: Example ADD R1,[2000H]) 5. For a jump instruction, the store step: A. Increments R1 B. Writes to flags only C. Updates the PC D. Fetches the opcode Answer: C. Jumps store the target by updating PC. (Key point: Store for jumps) ## Related in Embedded System - [ASIP versus general purpose processor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aasip-vs-gpp) — Embedded System, chapter 2 - [GPP operation: datapath and controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Agpp-datapath-controller) — Embedded System, chapter 2, asked 4× - [ASIP vs GPP and processor selection](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aasip-vs-gpp-selection-issues) — Embedded System, chapter 2 - [Datapath operation and instruction cycles](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adatapath-operation-instruction-cycles) — Embedded System, chapter 2 - [Single-purpose processor for power](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-power) — Embedded System, chapter 2, asked 2× - [Dual-purpose processor: median and variance](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Adual-purpose-median-variance) — Embedded System, chapter 2 ## Related in other subjects - [Data structure and basic operations](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Adata-structure-basic-operations) — Data Structure and Algorithm, chapter 1 - [Linked list and its basic operations](https://www.bctengineer.com/question.md?key=semester_4%2Fdata_structure_and_algorithm%3Alinked-list-and-operations) — Data Structure and Algorithm, chapter 4 - [General block diagram of a control system](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Ageneral-bd-control-system) — Control Systems, chapter 1 - [Basic lathe operations](https://www.bctengineer.com/question.md?key=semester_2%2Fworkshop_technology%3Alathe-operations-explained) — Workshop Technology, chapter 6