---
title: "Datapath operation and instruction cycles"
subject: "Embedded System"
chapter: 2
key: "semester_6/embedded_system:datapath-operation-instruction-cycles"
source: https://www.bctengineer.com/q/semester_6/embedded_system/datapath-operation-instruction-cycles
site: BCT Engineering
---

# Datapath operation and instruction cycles

Embedded System · Chapter 2: Hardware Design Issues

- Asked in: 2072 Asoj, 4 marks
- Video: [Data Path](https://www.youtube.com/watch?v=0RMHamOq5FA) — TutorialsPoint
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/datapath-operation-instruction-cycles
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-2

## Question

Explain the data path operation and its instruction cycles.

## Short answer

The datapath uses ALU, registers, and buses to execute operations: operands fetched, ALU selected, result stored. The instruction cycle consists of fetch, decode, operand fetch, execute, and store result, repeating for each instruction. Status flags inform the controller for conditional actions.

## Answer

The **datapath** of a processor contains the registers, ALU and buses that carry out computation under the control unit's signals. Its operation is organised into the **instruction cycle**.

#### Datapath operation
Operands come from registers (or memory) onto the ALU inputs, the ALU executes the selected function (add, subtract, AND, shift, compare), and the result goes back to a register or memory. Status flags (zero, carry, sign) go to the controller.

```text
 Register file --> [ALU] --> Result bus --> Register file
        ^            ^ function select
        |            |
   ----- control signals from controller -----
```

#### Instruction cycles (steps)
1. **Fetch:** the datapath sends PC to memory, IR <- instruction, PC <- PC + 1.
2. **Decode:** opcode decoded by the controller; registers/operand addresses chosen.
3. **Fetch operands:** read registers or memory into ALU input registers.
4. **Execute:** the ALU operates (or the address/branch is computed).
5. **Store result:** write result to register or memory.

Example: ADD R1, R2, R3: fetch the instruction, decode, read R2 and R3, the ALU adds, then R1 <- sum. The cycle then repeats for the next instruction.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does the datapath operate?
   A. The datapath decodes opcodes
   B. Operands go to the ALU, which executes the selected function and the result returns to a register or memory
   C. It generates control signals
   D. It stores firmware
   Answer: B. The ALU executes under control signals and status flags go to the controller. (Key point: Datapath operation)

2. Where do status flags (zero, carry, sign) go?
   A. To the sensors
   B. To the keyboard
   C. To the controller
   D. Nowhere
   Answer: C. Flags let the controller decide branches. (Key point: Status flags)

3. What is the order of the instruction cycle?
   A. Decode, store, fetch, execute
   B. Execute, fetch, store, decode
   C. Store, fetch, decode, execute
   D. Fetch, decode, fetch operands, execute, store
   Answer: D. Fetch the instruction, decode, read operands, execute, then store the result. (Key point: Instruction steps)

4. In ADD R1, R2, R3, after the ALU adds R2 and R3, what happens?
   A. R1 <- sum
   B. R2 <- sum
   C. PC <- sum
   D. Memory is cleared
   Answer: A. The store step writes the sum into R1. (Key point: ADD R1,R2,R3)

## Related in Embedded System

- [GPP operation: datapath and controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Agpp-datapath-controller) — Embedded System, chapter 2, asked 4×
- [One Time Programmable ROM operation](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aotp-rom-storing) — Embedded System, chapter 4, asked 2×

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