--- title: "DMA controller and flow of actions" subject: "Embedded System" chapter: 5 key: "semester_6/embedded_system:dma-controller-flow" source: https://www.bctengineer.com/q/semester_6/embedded_system/dma-controller-flow site: BCT Engineering --- # DMA controller and flow of actions Embedded System · Chapter 5: Interfacing - Asked in: 2070 Magh, 2+2 marks; 2079 Jestha, 4 marks; 2064 Poush (old course) (asked 3 times) - Video: [Computer Organization #68: Full Concept of DMA | Direct Memory Access | DMA | Modes of DMA Transfer](https://www.youtube.com/watch?v=qiaEGFh4D_I) — Vinay Mishra - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/dma-controller-flow - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5 ## Question Describe the purpose of the direct-memory-access (DMA) controller. Draw the flow of actions between peripheral and memory (peripheral to memory transfer) using DMA, with block diagram. ## Short answer A DMA controller transfers data blocks directly between peripheral and memory, bypassing CPU per byte. CPU sets up start address, byte count, and direction. On peripheral request, the DMA controller gains bus control, writes each data byte to memory, updates address and count, and signals completion via an interrupt. ## Answer #### Purpose of the DMA controller A **direct memory access (DMA) controller** transfers blocks of data directly between a peripheral and memory without the processor handling each byte. The processor only sets up the transfer (starting address, number of bytes, direction); the DMA controller then takes the bus and performs the transfers itself. This frees the CPU for other work, gives much higher transfer rates than interrupt-driven or polled I/O, and avoids the overhead of ISR entry/exit for each word. #### Block diagram ```text +-----------+ Hold/Req +-------------+ Req/Ack +------------+ | Processor |<---------->| DMA |<---------->| Peripheral | | | Hlda/Ack | controller | +-----+------+ +-----+-----+ | (address | | | | reg, count | | | | reg, ctrl) | | | +------+------+ | ======+==================== Address / Data / Control bus ==+==== | +----+-----+ | Memory | +----------+ ``` #### Flow of actions (peripheral to memory) 1. The processor is running its main program and sets up the DMA controller registers: starting memory address, byte count and direction (e.g. 100 for the address, 4 bytes), then continues its work. 2. The peripheral has data and asserts **Req** (DMA request) to the DMA controller. 3. The DMA controller asserts **Hold/Bus request** to the processor. 4. The processor finishes its current bus cycle, releases the address/data/control buses and sends **Hlda/Ack** (bus granted). 5. The DMA controller sends **Ack** to the peripheral and places the memory address on the address bus. 6. The peripheral places the data on the data bus; memory is written (M[address] = data) in one bus cycle. 7. The DMA controller increments the address and decrements the count. Steps 2 to 6 repeat until the count is zero. 8. The DMA controller releases the bus (drops Hold) and raises an **interrupt** to inform the processor that the transfer is complete; the processor resumes use of the bus. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. What is the purpose of a DMA controller? A. Transfer blocks between peripheral and memory without the processor handling each byte B. Decode instructions C. Refresh DRAM D. Replace the ALU Answer: A. The CPU only sets up the transfer; the DMA controller does it, freeing the CPU. (Key point: Purpose of DMA) 2. What does the processor program into the DMA controller initially? A. Starting address, byte count and direction B. The data itself C. Interrupt vectors D. The ISR code Answer: A. Address, count and direction registers are set, then the processor continues its work. (Key point: Setup) 3. After the peripheral's Req, what does the DMA controller send to the processor? A. Hold/bus request, answered by Hlda B. An interrupt vector C. Inta D. A reset Answer: A. The processor finishes its bus cycle, releases the buses and returns Hlda. (Key point: Bus handshake) 4. What happens when the count reaches zero? A. DMA releases the bus and interrupts the processor B. The processor polls DMA C. DMA restarts D. Memory is cleared Answer: A. After each transfer the address increments and count decrements; at zero the controller drops Hold and raises an interrupt. (Key point: Completion) ## Related in Embedded System - [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5 - [PID control operation with block diagram](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apid-operation-block-diagram) — Embedded System, chapter 7, asked 4× - [Arbitration and memory-mapped vs standard I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aarbitration-memory-mapped-io) — Embedded System, chapter 5 - [Cache memory mapping techniques](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acache-mapping-techniques) — Embedded System, chapter 4, asked 3× - [GPP operation: datapath and controller](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Agpp-datapath-controller) — Embedded System, chapter 2, asked 4× - [Single-purpose processor for power](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aspp-power) — Embedded System, chapter 2, asked 2× ## Related in other subjects - [DMA controller block diagram and transfer](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adma-controller) — Computer Organization and Architecture, chapter 7, asked 6× - [PID controller block diagram, transfer function, characteristics](https://www.bctengineer.com/question.md?key=semester_3%2Fcontrol_systems%3Apid-bd-tf-characteristics) — Control Systems, chapter 7 - [MBI block diagram, advantages and DMA](https://www.bctengineer.com/question.md?key=semester_5%2Finstrumentation_ii%3Ambi-block-advantages-dma) — Instrumentation II, chapter 1 - [Direct mapping with 32-block memory, 8-block cache](https://www.bctengineer.com/question.md?key=semester_5%2Fcomputer_organization_and_architecture%3Adirect-mapping-example) — Computer Organization and Architecture, chapter 6, asked 3×