---
title: "Enhanced DRAM core"
subject: "Embedded System"
chapter: 4
key: "semester_6/embedded_system:enhanced-dram"
source: https://www.bctengineer.com/q/semester_6/embedded_system/enhanced-dram
site: BCT Engineering
---

# Enhanced DRAM core

Embedded System · Chapter 4: Memory

- Asked in: 2071 Magh, 5 marks
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/enhanced-dram
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-4

## Question

What is enhanced DRAM built around the conventional DRAM core?

## Short answer

Enhanced DRAM adds circuits around the conventional DRAM core to exploit the row buffer read into sense amplifiers, enabling faster access modes like Fast Page Mode, EDO, SDRAM, DDR SDRAM, and cache DRAM without changing the cell array.

## Answer

A conventional DRAM core (an array of capacitor cells with row and column decoders and sense amplifiers) is slow because each access has to read a whole row and then precharge. **Enhanced DRAM** improves speed without changing the DRAM cell array. It adds circuits around the core that exploit the fact that a whole row is read into the sense amplifiers at once.

#### Enhancements around the DRAM core
- **Fast Page Mode (FPM) DRAM:** after a row is opened, several column addresses in the same row are accessed without re-sending the row address, which speeds up sequential access.
- **EDO (Extended Data Out) DRAM:** the output data is latched and stays valid while the next column address is applied, so successive reads overlap and are faster.
- **Synchronous DRAM (SDRAM):** a clock synchronises the memory with the system bus, allowing pipelined, burst transfers.
- **DDR SDRAM:** transfers data on both clock edges, doubling the data rate.
- **Rambus DRAM (RDRAM):** uses a narrow, high-speed, packet-based bus.
- **Cache (Enhanced) DRAM, EDRAM:** a small SRAM cache on the chip holds the last accessed row; hits are served at SRAM speed, and the DRAM core is accessed only on misses.

```text
 Address -> [Row/col decoders] -> [DRAM array core]
                                       |
                              [Sense amps + row SRAM buffer]
                                       |
                                    Data out (burst)
```
All of these give faster access to consecutive data by using the row buffer around the core, at a modest extra cost.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. How does enhanced DRAM improve speed?
   A. By replacing the capacitor cell array
   B. By adding circuits around the DRAM core that exploit a whole row being read into the sense amplifiers
   C. By removing refresh
   D. By using flip-flop cells
   Answer: B. The cell array is unchanged; extra circuits exploit the row held in the sense amplifiers. (Key point: Idea of enhanced DRAM)

2. What does Fast Page Mode DRAM do?
   A. Accesses several columns of an open row without re-sending the row address
   B. Transfers on both clock edges
   C. Uses a packet-based bus
   D. Adds an SRAM to the chip
   Answer: A. After a row is opened, multiple column addresses in the same row are accessed quickly. (Key point: Fast Page Mode)

3. What distinguishes DDR SDRAM?
   A. It transfers data on both clock edges
   B. It needs no clock
   C. It uses a narrow packet bus
   D. It latches output only
   Answer: A. DDR transfers on both rising and falling clock edges, doubling the data rate. (Key point: DDR)

4. In cache (enhanced) DRAM, what does the on-chip SRAM hold?
   A. The refresh counter
   B. The last accessed row
   C. The whole array
   D. The row decoder
   Answer: B. Hits in this SRAM are served at SRAM speed; the DRAM core is accessed only on misses. (Key point: Cache DRAM)

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