---
title: "IC manufacturing steps; top-down F = xz + y"
subject: "Embedded System"
chapter: 8
key: "semester_6/embedded_system:ic-manufacturing-steps-topdown-xz-y"
source: https://www.bctengineer.com/q/semester_6/embedded_system/ic-manufacturing-steps-topdown-xz-y
site: BCT Engineering
---

# IC manufacturing steps; top-down F = xz + y

Embedded System · Chapter 8: IC Technology

- Asked in: 2070 Bhadra, 4+4 marks
- Video: [How are BILLIONS of MICROCHIPS made from SAND? | How are SILICON WAFERS made?](https://www.youtube.com/watch?v=52GoRYP1les) — Xprocess
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/ic-manufacturing-steps-topdown-xz-y
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-8

## Question

Describe the steps involved in manufacturing an IC. Show the top-down view of the circuit F = xz + y on an IC.

## Short answer

IC fabrication: wafer preparation, oxidation, photolithography, etching, doping, metallisation, repeating for each layer; then testing and packaging. F = xz + y is realized by F = NOT(G) with G = NOT(xz+y); pull-down: y || (x series z), pull-up: y series (x||z), 8 transistors.

## Answer

#### Steps to manufacture an IC

1. **Wafer preparation:** purify silicon, grow a single crystal (Czochralski), slice, polish, clean.
2. **Oxidation:** grow a SiO2 layer on the wafer.
3. **Photolithography:** coat photoresist, align the mask, expose and develop.
4. **Etching:** remove the oxide or film in the exposed windows.
5. **Doping:** diffusion or ion implantation to make wells and source/drain regions.
6. **Gate formation:** thin gate oxide and polysilicon gates, patterned by lithography.
7. **Deposition and metallisation:** insulating layers, contacts and metal interconnect layers.
8. **Repeat** steps 2-7 for every mask layer.
9. **Wafer test, dicing, packaging and final test.**

#### Top-down view of F = xz + y

F is made as F = NOT(G), where G = NOT(xz + y).

```text
VDD ---+-------------+
       |             |
    PMOS(x)       PMOS(z)      x, z in parallel
       |             |
       +------+------+
              |
           PMOS(y)             in series with y
              |
              +-----------------> G --[INV]--> F
              |
       +------+------+
       |             |
    NMOS(y)       NMOS(x)      y in parallel with
       |             |         (x in series with z)
      GND         NMOS(z)
                     |
                    GND
```

Pull-down: y in parallel with (x series z). Pull-up: y in series with (x parallel z). Total 8 transistors with the output inverter.

Top-down (stick) layout:

```text
 VDD ================================ metal
       |    |    |
     +-+----+----+-+  p+ diffusion
     |  x    z    y |  vertical poly
     +-+----+----+-+  lines cross
       +---- G ----   metal output
     +-+----+----+-+  both rows
     |  x    z    y |  n+ diffusion
     +-+----+----+-+
       |    |    |
 GND ================================ metal
```

Each poly-diffusion crossing forms a transistor; metal and contacts connect the drains to G, the sources to VDD/GND, and G to the output inverter (not shown).

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Which method is named for growing the single-crystal silicon before slicing the wafer?
   A. Czochralski
   B. Sputtering
   C. LOCOS
   D. Wire bonding
   Answer: A. The Czochralski process grows the single-crystal ingot that is sliced, polished and cleaned. (Key point: Wafer preparation)

2. In the process sequence, what follows photolithography (coat, align, expose, develop)?
   A. Dicing
   B. Etching of the film in the exposed windows
   C. Wafer growth
   D. Packaging
   Answer: B. Etching removes the oxide or film in the openings defined by the developed resist. (Key point: Step order)

3. Why are steps 2-7 repeated?
   A. To thicken the wafer
   B. To remove defects
   C. Each mask layer needs its own oxidation/pattern/doping/deposition cycle
   D. To test each die
   Answer: C. The IC is built layer by layer, with one cycle for every mask layer. (Key point: Layer repetition)

4. For G = NOT(xz + y), how are the NMOS pull-down transistors connected?
   A. All three in series
   B. y in series with (x parallel z)
   C. x, y and z all in parallel
   D. y in parallel with (x in series with z)
   Answer: D. The AND term xz is a series pair; the OR with y puts y in parallel with it. The pull-up is the dual. (Key point: Gate F = xz + y)

## Related in Embedded System

- [Top-down view for F = xz + yz'](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Apositive-photoresist-topdown-xz-yzbar) — Embedded System, chapter 8
- [IC manufacturing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aic-manufacturing-steps) — Embedded System, chapter 8
- [IC manufacturing, alignment and exposure](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aphotolithography-alignment-exposure) — Embedded System, chapter 8
- [Semi-custom ASIC and manufacturing steps](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Asemi-custom-asic-types-manufacturing) — Embedded System, chapter 8

## Related in other subjects

- [Top-down approach](https://www.bctengineer.com/question.md?key=semester_5%2Fsoftware_engineering%3Atop-down-approach) — Software Engineering, chapter 3
- [Top-down integration problems; regression testing](https://www.bctengineer.com/question.md?key=semester_5%2Fsoftware_engineering%3Atop-down-integration-regression) — Software Engineering, chapter 8