--- title: "Interface circuit with 2 RAMs and 2 ROMs" subject: "Embedded System" chapter: 5 key: "semester_6/embedded_system:interface-circuit-16bit-ram-rom" source: https://www.bctengineer.com/q/semester_6/embedded_system/interface-circuit-16bit-ram-rom site: BCT Engineering --- # Interface circuit with 2 RAMs and 2 ROMs Embedded System · Chapter 5: Interfacing - Asked in: 2073 Magh, 8 marks - Video: [Memory Interfacing of two 8Kbyte ROM & 1Kbyte RAM](https://www.youtube.com/watch?v=qzl9WMmoshg) — Jay Guru Explains - Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14 - Page: https://www.bctengineer.com/q/semester_6/embedded_system/interface-circuit-16bit-ram-rom - Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5 ## Question Design an interface circuit of a microprocessor with 16-bit address with 2 RAMs and 2 ROMs of 8 Kbyte each. ## Short answer Use a 2-to-4 decoder with A15 enabling, A14 and A13 as selects. ROM1 is selected at 0000H–1FFFH, ROM2 at 2000H–3FFFH, RAM1 at 4000H–5FFFH, RAM2 at 6000H–7FFFH. All chips share A12–A0, RD, and the data bus; WR strobes only the RAMs. ## Answer **Given:** a processor with a 16-bit address bus (64 KB space) and an 8-bit data bus, and four chips of 8 KB each: ROM1, ROM2, RAM1, RAM2. #### Address lines 8 KB = 2^13 bytes, so each chip needs **13 address lines (A12-A0)**, connected in parallel to all chips. The remaining lines A15, A14 and A13 are used for **chip selection**. With four chips (32 KB in total), A14 and A13 select one chip, and A15 enables the decoder (the memory occupies the lower 32 KB). #### Chip-select logic A 2-to-4 decoder (e.g. 74LS139) is used, with its active-low enable input G' driven by A15. | A15 | A14 | A13 | Chip selected | Address range | |---|---|---|---|---| | 0 | 0 | 0 | ROM1 | 0000H - 1FFFH | | 0 | 0 | 1 | ROM2 | 2000H - 3FFFH | | 0 | 1 | 0 | RAM1 | 4000H - 5FFFH | | 0 | 1 | 1 | RAM2 | 6000H - 7FFFH | | 1 | x | x | none | 8000H - FFFFH (free) | #### Circuit ```text +-------------------------------+ A12..A0 -----+--> A of ROM1, ROM2, RAM1, RAM2 | +-------------------------------+ A15 ------> G' +-----------+ A14 ------> B | 2-to-4 |--Y0'--> CS' ROM1 A13 ------> A | decoder |--Y1'--> CS' ROM2 | |--Y2'--> CS' RAM1 +-----------+--Y3'--> CS' RAM2 RD' -------> OE' of all four chips WR' -------> WE' of RAM1 and RAM2 only (ROMs are read-only) D7..D0 <===> data pins of every chip (tri-state, shared) ``` **Operation:** when the processor outputs an address, A15 = 0 enables the decoder, and A14A13 activates the chip select of exactly one chip. Only that chip drives the data bus (read) or latches it (RAM write), using A12-A0 for the location within the chip. RD' and WR' act as the read and write strobes. The ROMs hold the program (booting from 0000H) and the RAMs hold data and the stack. ## Check yourself The answer's key points as multiple-choice questions, with the correct option and why. 1. How many address lines does an 8 KB chip need and which? A. 10 lines, A9-A0 B. 13 lines, A12-A0, in parallel to all chips C. 8 lines, A7-A0 D. 16 lines, A15-A0 Answer: B. 8 KB = 2^13 bytes, so 13 lines; A15, A14, A13 are left for chip selection. (Key point: Address lines per chip) 2. How are the four chips selected? A. All chips are selected together B. The data bus selects the chip C. A15 and A14 drive the decoder; A13 enables D. A 2-to-4 decoder driven by A14 and A13, enabled by A15 = 0 Answer: D. A15 = 0 enables the decoder and A14A13 activates exactly one chip select. (Key point: Decoder usage) 3. What is the address range of RAM1? A. 2000H - 3FFFH B. 6000H - 7FFFH C. 0000H - 1FFFH D. 4000H - 5FFFH Answer: D. A15A14A13 = 010 gives 4000H-5FFFH; ROM1 is 0000-1FFF, ROM2 2000-3FFF, RAM2 6000-7FFF. (Key point: Address map) 4. How are RD' and WR' connected? A. RD' to RAMs only B. WR' to ROMs only C. WR' to all four chips D. RD' to OE' of all four chips; WR' to WE' of the RAMs only Answer: D. ROMs are read-only so they have no write enable. (Key point: Control signals) ## Related in Embedded System - [Compose 1K x 8 ROMs into 2K x 16](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx8) — Embedded System, chapter 4, asked 2× - [How interrupts interface with microprocessor](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-interface-microprocessor) — Embedded System, chapter 5 - [Compose 2K x 16 ROM using 1K x 4](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-2kx16-from-1kx4) — Embedded System, chapter 4 - [Compose 4K x 16 ROM using 1K x 8](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Acompose-4kx16-from-1kx8) — Embedded System, chapter 4 - [Structural modelling; 3-bit up counter](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Avhdl-structural-3bit-counter) — Embedded System, chapter 9 ## Related in other subjects - [8085 ALP: compare two tables of 16-bit data](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8085-compare-tables-1ffffh) — Microprocessor, chapter 2 - [8086 ALP: max and min of 16-bit list](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aalp-8086-max-min-16bit) — Microprocessor, chapter 3 - [Circuit giving 2's complement of a 4-bit number](https://www.bctengineer.com/question.md?key=semester_3%2Fdigital_logic%3Atwos-complement-generator) — Digital Logic, chapter 5 - [Interface two 8K x 8 ROM at 4000H](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Adecoder-two-8k-rom-4000h) — Microprocessor, chapter 4