---
title: "How interrupts interface with microprocessor"
subject: "Embedded System"
chapter: 5
key: "semester_6/embedded_system:interrupt-interface-microprocessor"
source: https://www.bctengineer.com/q/semester_6/embedded_system/interrupt-interface-microprocessor
site: BCT Engineering
---

# How interrupts interface with microprocessor

Embedded System · Chapter 5: Interfacing

- Asked in: 2079 Jestha, 4 marks
- Video: [How Interrupts Work in Modern Computers](https://www.youtube.com/watch?v=G7bqvpAw7HE) — BitLemon
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/interrupt-interface-microprocessor
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5

## Question

How do interrupts interface with a microprocessor? Explain it.

## Short answer

Peripherals connect to the microprocessor through an interrupt controller like the 8259 PIC, which manages multiple IRQ lines, priority, and masking. The controller asserts INT to the CPU; when the CPU sends INTA, the controller places the interrupt vector on the data bus, allowing the CPU to fetch the ISR address from the IVT.

## Answer

A microprocessor has one or a few interrupt input pins (such as INTR, NMI), while a system has many devices that can interrupt. The devices are connected to the processor through an **interrupt controller** (e.g. the Intel 8259 PIC).

```text
 Device 0 -- IRQ0 --+
 Device 1 -- IRQ1 --+--> +-------------+  INT   +-----------+
 Device 2 -- IRQ2 --+    | Interrupt   |------->|           |
   ...                   | controller  |  INTA  | Micro-    |
 Device 7 -- IRQ7 --+    | (priority,  |<-------| processor |
                         |  mask)      |  D0-D7 |           |
                         +------+------+<======>+-----------+
                                (vector on data bus)
```

#### Operation
1. A device raises its IRQ line. The controller checks the mask and priority and sends **INT** to the processor.
2. The processor finishes the current instruction, saves the PC and flags on the stack, and sends **INTA**.
3. The controller puts the interrupt **vector number** (or the call instruction with the ISR address) on the data bus.
4. The processor uses the vector to look up the **IVT**, loads the ISR address into the PC and runs the ISR.
5. At the end, a return-from-interrupt instruction (IRET/RETI) restores the PC and flags and the main program continues.

The interrupt controller thus provides many interrupt lines, priority resolution, masking and the vector, and so interfaces many devices with the single INT pin. **Non-maskable interrupt (NMI)** cannot be disabled and is used for critical events such as power failure.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. Why is an interrupt controller such as the 8259 PIC used?
   A. The processor has few interrupt pins but many devices can interrupt
   B. To increase the clock speed
   C. The processor has no interrupt capability
   D. To store the ISRs
   Answer: A. The controller connects many devices to the single INT pin. (Key point: Need for interrupt controller)

2. Which functions does the interrupt controller provide?
   A. DMA transfers
   B. Address decoding for memory
   C. Priority resolution, masking, and supplying the vector
   D. Only data storage
   Answer: C. It provides many lines, priority, masking and the vector. (Key point: Controller functions)

3. After the processor sends INTA, what does the controller do?
   A. Loads the PC itself
   B. Resets the devices
   C. Puts the vector number on the data bus
   D. Sends INT again
   Answer: C. The processor uses the vector to look up the IVT and run the ISR. (Key point: Interrupt sequence)

4. What is special about the non-maskable interrupt (NMI)?
   A. It needs the 8259
   B. It is ignored in ISRs
   C. It cannot be disabled and is used for critical events such as power failure
   D. It is the lowest priority
   Answer: C. NMI cannot be masked. (Key point: NMI)

## Related in Embedded System

- [Interface circuit with 2 RAMs and 2 ROMs](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterface-circuit-16bit-ram-rom) — Embedded System, chapter 5

## Related in other subjects

- [Maskable vs non-maskable interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Amaskable-vs-nonmaskable) — Microprocessor, chapter 5, asked 2×
- [Software interrupts of 8085](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8085-software-interrupts) — Microprocessor, chapter 5
- [Hardware interrupts available in 8086](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3A8086-hardware-interrupts) — Microprocessor, chapter 5
- [Hardware vs software interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Ahardware-vs-software-interrupts) — Microprocessor, chapter 5