---
title: "IRQ, ISR, IVT, PUSH, POP, latency"
subject: "Embedded System"
chapter: 5
key: "semester_6/embedded_system:interrupt-terms-irq-isr-ivt"
source: https://www.bctengineer.com/q/semester_6/embedded_system/interrupt-terms-irq-isr-ivt
site: BCT Engineering
---

# IRQ, ISR, IVT, PUSH, POP, latency

Embedded System · Chapter 5: Interfacing

- Asked in: 2064 Poush (old course)
- Video: [How Interrupts Work in Modern Computers](https://www.youtube.com/watch?v=G7bqvpAw7HE) — BitLemon
- Answer checked by Claude Opus 5.5 (high effort) on 2026-10-14
- Page: https://www.bctengineer.com/q/semester_6/embedded_system/interrupt-terms-irq-isr-ivt
- Whole chapter: https://www.bctengineer.com/md/semester_6/embedded_system/chapter-5

## Question

Describe the terms IRQ, ISR, IVT, PUSH, POP and Interrupt Latency used in Interrupt based designs.

## Short answer

IRQ: interrupt request signal. ISR: interrupt service routine handling the IRQ. IVT: table mapping each interrupt number to its ISR start address. PUSH and POP save and restore context on the stack. Interrupt latency is the time from IRQ assertion to the first ISR instruction.

## Answer

- **IRQ (Interrupt Request):** the signal (hardware line) from a peripheral or internal event asking the processor to stop its current work and service the device. Each source has an IRQ line (IRQ0, IRQ1, ...) that may be masked and prioritised.
- **ISR (Interrupt Service Routine):** the software routine executed in response to an interrupt. It services the device (reads data, clears the flag) and ends with a return-from-interrupt instruction. It should be short.
- **IVT (Interrupt Vector Table):** a table in memory (often at the start, e.g. 00000H-003FFH in the 8086) holding the starting addresses (vectors) of all ISRs. The interrupt number indexes the table to find the ISR address.
- **PUSH:** stores a register (or the PC and flags) on the stack and decrements SP. It is used to save the context at ISR entry.
- **POP:** reads the top of the stack back into a register (or the PC/flags) and increments SP. It is used to restore the context before returning.
- **Interrupt latency:** the time from the occurrence of the interrupt request to the execution of the first instruction of its ISR. It includes finishing the current instruction, recognising the request, saving the context and fetching the vector. Low and predictable latency is vital in real-time systems; it grows with periods when interrupts are disabled and with higher-priority ISRs.

## Check yourself

The answer's key points as multiple-choice questions, with the correct option and why.

1. What is the difference between IRQ and ISR?
   A. Both are tables
   B. IRQ is software; ISR is hardware
   C. IRQ is a stack operation
   D. IRQ is the request signal from a device; ISR is the software routine that services it
   Answer: D. IRQ is the hardware line; ISR services the device and ends with return-from-interrupt. (Key point: IRQ vs ISR)

2. What does the IVT hold?
   A. Starting addresses (vectors) of all ISRs, indexed by interrupt number
   B. Device status flags
   C. Stack data
   D. Register contents
   Answer: A. For example, 0000H-03FFH in the 8086. (Key point: IVT)

3. What happens to SP in PUSH and POP?
   A. PUSH decrements SP, POP increments SP
   B. PUSH increments SP, POP decrements SP
   C. Both clear SP
   D. Both leave SP unchanged
   Answer: A. PUSH stores onto the stack (SP decremented); POP reads back (SP incremented). (Key point: PUSH and POP)

4. What is interrupt latency?
   A. Time to execute the whole ISR
   B. Time between two interrupts
   C. Time from the interrupt request to execution of the first instruction of its ISR
   D. Time to reset the processor
   Answer: C. It grows with disabled-interrupt periods and higher-priority ISRs; low latency is vital in real time. (Key point: Interrupt latency)

## Related in Embedded System

- [Interrupt and fixed ISR flow of actions](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Ainterrupt-fixed-isr-flow) — Embedded System, chapter 5
- [Port-based and bus-based I/O](https://www.bctengineer.com/question.md?key=semester_6%2Fembedded_system%3Aport-based-vs-bus-based-io) — Embedded System, chapter 5, asked 2×

## Related in other subjects

- [ISR, IVT and type 0 to 4 interrupts](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-ir-isr-type-0-to-4) — Microprocessor, chapter 5
- [IVT in 8086 and ISR execution sequence](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Aivt-8086-isr-execution-sequence) — Microprocessor, chapter 5
- [PC and SP in CALL, RET, PUSH, POP](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Apc-sp-call-ret-push-pop) — Microprocessor, chapter 2
- [Compare CALL/RET with PUSH/POP](https://www.bctengineer.com/question.md?key=semester_4%2Fmicroprocessor%3Acall-ret-vs-push-pop) — Microprocessor, chapter 2